1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <fdt_support.h>
9 #include <hang.h>
10 #include <i2c.h>
11 #include <asm/cache.h>
12 #include <init.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #ifdef CONFIG_FSL_LS_PPA
18 #include <asm/arch/ppa.h>
19 #endif
20 #include <asm/arch/mmu.h>
21 #include <asm/arch/soc.h>
22 #include <hwconfig.h>
23 #include <ahci.h>
24 #include <mmc.h>
25 #include <scsi.h>
26 #include <fsl_esdhc.h>
27 #include <env_internal.h>
28 #include <fsl_mmdc.h>
29 #include <netdev.h>
30 #include <fsl_sec.h>
31 #include <net/pfe_eth/pfe/pfe_hw.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define BOOT_FROM_UPPER_BANK 0x2
36 #define BOOT_FROM_LOWER_BANK 0x1
37
checkboard(void)38 int checkboard(void)
39 {
40 #ifdef CONFIG_TARGET_LS1012ARDB
41 u8 in1;
42 int ret, bus_num = 0;
43
44 puts("Board: LS1012ARDB ");
45
46 /* Initialize i2c early for Serial flash bank information */
47 #if CONFIG_IS_ENABLED(DM_I2C)
48 struct udevice *dev;
49
50 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
51 1, &dev);
52 if (ret) {
53 printf("%s: Cannot find udev for a bus %d\n", __func__,
54 bus_num);
55 return -ENXIO;
56 }
57 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
58 #else /* Non DM I2C support - will be removed */
59 i2c_set_bus_num(bus_num);
60 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
61 #endif
62 if (ret < 0) {
63 printf("Error reading i2c boot information!\n");
64 return 0; /* Don't want to hang() on this error */
65 }
66
67 puts("Version");
68 switch (in1 & SW_REV_MASK) {
69 case SW_REV_A:
70 puts(": RevA");
71 break;
72 case SW_REV_B:
73 puts(": RevB");
74 break;
75 case SW_REV_C:
76 puts(": RevC");
77 break;
78 case SW_REV_C1:
79 puts(": RevC1");
80 break;
81 case SW_REV_C2:
82 puts(": RevC2");
83 break;
84 case SW_REV_D:
85 puts(": RevD");
86 break;
87 case SW_REV_E:
88 puts(": RevE");
89 break;
90 default:
91 puts(": unknown");
92 break;
93 }
94
95 printf(", boot from QSPI");
96 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
97 puts(": emu\n");
98 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
99 puts(": bank1\n");
100 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
101 puts(": bank2\n");
102 else
103 puts("unknown\n");
104 #else
105
106 puts("Board: LS1012A2G5RDB ");
107 #endif
108 return 0;
109 }
110
111 #ifdef CONFIG_TFABOOT
dram_init(void)112 int dram_init(void)
113 {
114 gd->ram_size = tfa_get_dram_size();
115 if (!gd->ram_size)
116 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
117
118 return 0;
119 }
120 #else
dram_init(void)121 int dram_init(void)
122 {
123 #ifndef CONFIG_TFABOOT
124 static const struct fsl_mmdc_info mparam = {
125 0x05180000, /* mdctl */
126 0x00030035, /* mdpdc */
127 0x12554000, /* mdotc */
128 0xbabf7954, /* mdcfg0 */
129 0xdb328f64, /* mdcfg1 */
130 0x01ff00db, /* mdcfg2 */
131 0x00001680, /* mdmisc */
132 0x0f3c8000, /* mdref */
133 0x00002000, /* mdrwd */
134 0x00bf1023, /* mdor */
135 0x0000003f, /* mdasp */
136 0x0000022a, /* mpodtctrl */
137 0xa1390003, /* mpzqhwctrl */
138 };
139
140 mmdc_init(&mparam);
141 #endif
142
143 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
144 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
145 /* This will break-before-make MMU for DDR */
146 update_early_mmu_table();
147 #endif
148
149 return 0;
150 }
151 #endif
152
153
board_early_init_f(void)154 int board_early_init_f(void)
155 {
156 fsl_lsch2_early_init_f();
157
158 return 0;
159 }
160
board_init(void)161 int board_init(void)
162 {
163 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
164 CONFIG_SYS_CCI400_OFFSET);
165 /*
166 * Set CCI-400 control override register to enable barrier
167 * transaction
168 */
169 if (current_el() == 3)
170 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
171
172 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
173 erratum_a010315();
174 #endif
175
176 #ifdef CONFIG_FSL_CAAM
177 sec_init();
178 #endif
179
180 #ifdef CONFIG_FSL_LS_PPA
181 ppa_init();
182 #endif
183 return 0;
184 }
185
186 #ifdef CONFIG_FSL_PFE
board_quiesce_devices(void)187 void board_quiesce_devices(void)
188 {
189 pfe_command_stop(0, NULL);
190 }
191 #endif
192
193 #ifdef CONFIG_TARGET_LS1012ARDB
esdhc_status_fixup(void * blob,const char * compat)194 int esdhc_status_fixup(void *blob, const char *compat)
195 {
196 char esdhc1_path[] = "/soc/esdhc@1580000";
197 bool sdhc2_en = false;
198 u8 mux_sdhc2;
199 u8 io = 0;
200 int ret, bus_num = 0;
201
202 #if CONFIG_IS_ENABLED(DM_I2C)
203 struct udevice *dev;
204
205 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
206 1, &dev);
207 if (ret) {
208 printf("%s: Cannot find udev for a bus %d\n", __func__,
209 bus_num);
210 return -ENXIO;
211 }
212 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
213 #else
214 i2c_set_bus_num(bus_num);
215 /* IO1[7:3] is the field of board revision info. */
216 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
217 #endif
218 if (ret < 0) {
219 printf("Error reading i2c boot information!\n");
220 return 0;
221 }
222
223 /* hwconfig method is used for RevD and later versions. */
224 if ((io & SW_REV_MASK) <= SW_REV_D) {
225 #ifdef CONFIG_HWCONFIG
226 if (hwconfig("esdhc1"))
227 sdhc2_en = true;
228 #endif
229 } else {
230 /*
231 * The I2C IO-expander for mux select is used to control
232 * the muxing of various onboard interfaces.
233 *
234 * IO0[3:2] indicates SDHC2 interface demultiplexer
235 * select lines.
236 * 00 - SDIO wifi
237 * 01 - GPIO (to Arduino)
238 * 10 - eMMC Memory
239 * 11 - SPI
240 */
241 #if CONFIG_IS_ENABLED(DM_I2C)
242 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
243 #else
244 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
245 #endif
246 if (ret < 0) {
247 printf("Error reading i2c boot information!\n");
248 return 0;
249 }
250
251 mux_sdhc2 = (io & 0x0c) >> 2;
252 /* Enable SDHC2 only when use SDIO wifi and eMMC */
253 if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
254 sdhc2_en = true;
255 }
256 if (sdhc2_en)
257 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
258 sizeof("okay"), 1);
259 else
260 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
261 sizeof("disabled"), 1);
262 return 0;
263 }
264 #endif
265
ft_board_setup(void * blob,struct bd_info * bd)266 int ft_board_setup(void *blob, struct bd_info *bd)
267 {
268 arch_fixup_fdt(blob);
269
270 ft_cpu_setup(blob, bd);
271
272 return 0;
273 }
274
switch_to_bank1(void)275 static int switch_to_bank1(void)
276 {
277 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
278 int ret, bus_num = 0;
279
280 #if CONFIG_IS_ENABLED(DM_I2C)
281 struct udevice *dev;
282
283 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
284 1, &dev);
285 if (ret) {
286 printf("%s: Cannot find udev for a bus %d\n", __func__,
287 bus_num);
288 return -ENXIO;
289 }
290 /*
291 * --------------------------------------------------------------------
292 * |bus |I2C address| Device | Notes |
293 * --------------------------------------------------------------------
294 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
295 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
296 * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
297 * | | | PCAL9555AHF | I2C bus |
298 * ----- --------------------------------------------------------------
299 * - mount three IO expander(PCAL9555AHF) on I2C1
300 *
301 * PCAL9555A device address
302 * slave address
303 * --------------------------------------
304 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
305 * --------------------------------------
306 * | fixed | hardware selectable|
307 *
308 * Output port 1(Pinter register bits = 0x03)
309 *
310 * P1_[7~0] = 0xf4
311 * P1_0 <---> CFG_MUX_QSPI_S0
312 * P1_1 <---> CFG_MUX_QSPI_S1
313 * CFG_MUX_QSPI_S[1:0] = 0b00
314 *
315 * QSPI chip-select demultiplexer select
316 * ---------------------------------------------------------------------
317 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
318 * ---------------------------------------------------------------------
319 * 0 | 0 |CS routed to SPI memory bank1(default)
320 * ---------------------------------------------------------------------
321 * 0 | 1 |CS routed to SPI memory bank2
322 * ---------------------------------------------------------------------
323 *
324 */
325 ret = dm_i2c_write(dev, offset_addr, &data, 1);
326 #else /* Non DM I2C support - will be removed */
327 i2c_set_bus_num(bus_num);
328 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
329 #endif
330
331 if (ret) {
332 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
333 chip_addr, offset_addr, data);
334 }
335
336 return ret;
337 }
338
switch_to_bank2(void)339 static int switch_to_bank2(void)
340 {
341 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
342 u8 chip_addr = 0x24;
343 int ret, i, bus_num = 0;
344
345 #if CONFIG_IS_ENABLED(DM_I2C)
346 struct udevice *dev;
347
348 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
349 1, &dev);
350 if (ret) {
351 printf("%s: Cannot find udev for a bus %d\n", __func__,
352 bus_num);
353 return -ENXIO;
354 }
355 #else /* Non DM I2C support - will be removed */
356 i2c_set_bus_num(bus_num);
357 #endif
358
359 /*
360 * 1th step: config port 1
361 * - the port 1 pin is enabled as an output
362 * 2th step: output port 1
363 * - P1_[7:0] output 0xf5,
364 * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
365 * CS routed to SPI memory bank2
366 */
367 for (i = 0; i < sizeof(data); i++) {
368 #if CONFIG_IS_ENABLED(DM_I2C)
369 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
370 #else /* Non DM I2C support - will be removed */
371 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
372 #endif
373 if (ret) {
374 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
375 chip_addr, offset_addr[i], data[i]);
376 goto err;
377 }
378 }
379
380 err:
381 return ret;
382 }
383
convert_flash_bank(int bank)384 static int convert_flash_bank(int bank)
385 {
386 int ret = 0;
387
388 switch (bank) {
389 case BOOT_FROM_UPPER_BANK:
390 ret = switch_to_bank2();
391 break;
392 case BOOT_FROM_LOWER_BANK:
393 ret = switch_to_bank1();
394 break;
395 default:
396 ret = CMD_RET_USAGE;
397 break;
398 };
399
400 return ret;
401 }
402
flash_bank_cmd(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])403 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
404 char *const argv[])
405 {
406 if (argc != 2)
407 return CMD_RET_USAGE;
408 if (strcmp(argv[1], "1") == 0)
409 convert_flash_bank(BOOT_FROM_LOWER_BANK);
410 else if (strcmp(argv[1], "2") == 0)
411 convert_flash_bank(BOOT_FROM_UPPER_BANK);
412 else
413 return CMD_RET_USAGE;
414
415 return 0;
416 }
417
418 U_BOOT_CMD(
419 boot_bank, 2, 0, flash_bank_cmd,
420 "Flash bank Selection Control",
421 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
422 );
423