1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2019 NXP
3 */
4 #include <common.h>
5 #include <clock_legacy.h>
6 #include <fdt_support.h>
7 #include <init.h>
8 #include <net.h>
9 #include <asm/arch-ls102xa/ls102xa_soc.h>
10 #include <asm/arch/ls102xa_devdis.h>
11 #include <asm/arch/immap_ls102xa.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 #include "../common/sleep.h"
17 #include <fsl_validate.h>
18 #include <fsl_immap.h>
19 #include <fsl_csu.h>
20 #include <netdev.h>
21 #include <spl.h>
22 #ifdef CONFIG_U_QE
23 #include <fsl_qe.h>
24 #endif
25
26 DECLARE_GLOBAL_DATA_PTR;
27
ddrmc_init(void)28 static void ddrmc_init(void)
29 {
30 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
31 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
32 u32 temp_sdram_cfg, tmp;
33
34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
35
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
38
39 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
40 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
42 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
43 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
44 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
45
46 #ifdef CONFIG_DEEP_SLEEP
47 if (is_warm_boot()) {
48 out_be32(&ddr->sdram_cfg_2,
49 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
50 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
51 out_be32(&ddr->init_ext_addr, (1 << 31));
52
53 /* DRAM VRef will not be trained */
54 out_be32(&ddr->ddr_cdr2,
55 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
56 } else
57 #endif
58 {
59 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
60 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
61 }
62
63 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
64 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
65
66 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
67
68 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
69
70 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
71 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
72
73 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
74
75 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
76 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
77
78 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
79
80 /* DDR erratum A-009942 */
81 tmp = in_be32(&ddr->debug[28]);
82 out_be32(&ddr->debug[28], tmp | 0x0070006f);
83
84 udelay(1);
85
86 #ifdef CONFIG_DEEP_SLEEP
87 if (is_warm_boot()) {
88 /* enter self-refresh */
89 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
90 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
91 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
92
93 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
94 } else
95 #endif
96 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
97
98 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
99
100 #ifdef CONFIG_DEEP_SLEEP
101 if (is_warm_boot()) {
102 /* exit self-refresh */
103 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
104 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
105 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
106 }
107 #endif
108 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
109 }
110
dram_init(void)111 int dram_init(void)
112 {
113 ddrmc_init();
114
115 erratum_a008850_post();
116
117 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
118
119 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
120 fsl_dp_resume();
121 #endif
122
123 return 0;
124 }
125
board_eth_init(struct bd_info * bis)126 int board_eth_init(struct bd_info *bis)
127 {
128 return pci_eth_init(bis);
129 }
130
board_early_init_f(void)131 int board_early_init_f(void)
132 {
133 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
134
135 #ifdef CONFIG_TSEC_ENET
136 /*
137 * Clear BD & FR bits for big endian BD's and frame data (aka set
138 * correct eTSEC endianness). This is crucial in ensuring that it does
139 * not report Data Parity Errors in its RX/TX FIFOs when attempting to
140 * send traffic.
141 */
142 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
143 /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
144 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
145 #endif
146
147 arch_soc_init();
148
149 #if defined(CONFIG_DEEP_SLEEP)
150 if (is_warm_boot()) {
151 timer_init();
152 dram_init();
153 }
154 #endif
155
156 return 0;
157 }
158
159 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)160 void board_init_f(ulong dummy)
161 {
162 void (*second_uboot)(void);
163
164 /* Clear the BSS */
165 memset(__bss_start, 0, __bss_end - __bss_start);
166
167 get_clocks();
168
169 #if defined(CONFIG_DEEP_SLEEP)
170 if (is_warm_boot())
171 fsl_dp_disable_console();
172 #endif
173
174 preloader_console_init();
175
176 dram_init();
177
178 /* Allow OCRAM access permission as R/W */
179 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
180 enable_layerscape_ns_access();
181 enable_layerscape_ns_access();
182 #endif
183
184 /*
185 * if it is woken up from deep sleep, then jump to second
186 * stage U-Boot and continue executing without recopying
187 * it from SD since it has already been reserved in memory
188 * in last boot.
189 */
190 if (is_warm_boot()) {
191 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
192 second_uboot();
193 }
194
195 board_init_r(NULL, 0);
196 }
197 #endif
198
board_init(void)199 int board_init(void)
200 {
201 #ifndef CONFIG_SYS_FSL_NO_SERDES
202 fsl_serdes_init();
203 #endif
204 ls102xa_smmu_stream_id_init();
205
206 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
207 enable_layerscape_ns_access();
208 #endif
209
210 #ifdef CONFIG_U_QE
211 u_qe_init();
212 #endif
213
214 return 0;
215 }
216
217 #if defined(CONFIG_SPL_BUILD)
spl_board_init(void)218 void spl_board_init(void)
219 {
220 ls102xa_smmu_stream_id_init();
221 }
222 #endif
223
224 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)225 int board_late_init(void)
226 {
227 #ifdef CONFIG_CHAIN_OF_TRUST
228 fsl_setenv_chain_of_trust();
229 #endif
230
231 return 0;
232 }
233 #endif
234
235 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)236 int misc_init_r(void)
237 {
238 #ifdef CONFIG_FSL_DEVICE_DISABLE
239 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
240 #endif
241
242 #ifdef CONFIG_FSL_CAAM
243 return sec_init();
244 #endif
245 }
246 #endif
247
248 #if defined(CONFIG_DEEP_SLEEP)
board_sleep_prepare(void)249 void board_sleep_prepare(void)
250 {
251 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
252 enable_layerscape_ns_access();
253 #endif
254 }
255 #endif
256
ft_board_setup(void * blob,struct bd_info * bd)257 int ft_board_setup(void *blob, struct bd_info *bd)
258 {
259 ft_cpu_setup(blob, bd);
260
261 #ifdef CONFIG_PCI
262 ft_pci_setup(blob, bd);
263 #endif
264
265 return 0;
266 }
267