1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2014 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <clock_legacy.h>
7 #include <console.h>
8 #include <env_internal.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <ns16550.h>
12 #include <nand.h>
13 #include <i2c.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <spi_flash.h>
17 #include <asm/global_data.h>
18 #include "../common/sleep.h"
19 #include "../common/spl.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
get_effective_memsize(void)23 phys_size_t get_effective_memsize(void)
24 {
25 return CONFIG_SYS_L3_SIZE;
26 }
27
get_board_sys_clk(void)28 unsigned long get_board_sys_clk(void)
29 {
30 return CONFIG_SYS_CLK_FREQ;
31 }
32
33 #if defined(CONFIG_SPL_MMC_BOOT)
34 #define GPIO1_SD_SEL 0x00020000
board_mmc_getcd(struct mmc * mmc)35 int board_mmc_getcd(struct mmc *mmc)
36 {
37 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
38 u32 val = in_be32(&pgpio->gpdat);
39
40 /* GPIO1_14, 0: eMMC, 1: SD */
41 val &= GPIO1_SD_SEL;
42
43 return val ? -1 : 1;
44 }
45
board_mmc_getwp(struct mmc * mmc)46 int board_mmc_getwp(struct mmc *mmc)
47 {
48 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
49 u32 val = in_be32(&pgpio->gpdat);
50
51 val &= GPIO1_SD_SEL;
52
53 return val ? -1 : 0;
54 }
55 #endif
56
board_init_f(ulong bootflag)57 void board_init_f(ulong bootflag)
58 {
59 u32 plat_ratio, sys_clk, ccb_clk;
60 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
61
62 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
63 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
64
65 /* Update GD pointer */
66 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
67
68 console_init_f();
69
70 #ifdef CONFIG_DEEP_SLEEP
71 /* disable the console if boot from deep sleep */
72 if (is_warm_boot())
73 fsl_dp_disable_console();
74 #endif
75
76 /* initialize selected port with appropriate baud rate */
77 sys_clk = get_board_sys_clk();
78 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
79 ccb_clk = sys_clk * plat_ratio / 2;
80
81 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
82 ccb_clk / 16 / CONFIG_BAUDRATE);
83
84 #if defined(CONFIG_SPL_MMC_BOOT)
85 puts("\nSD boot...\n");
86 #elif defined(CONFIG_SPL_SPI_BOOT)
87 puts("\nSPI boot...\n");
88 #elif defined(CONFIG_SPL_NAND_BOOT)
89 puts("\nNAND boot...\n");
90 #endif
91
92 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
93 }
94
board_init_r(gd_t * gd,ulong dest_addr)95 void board_init_r(gd_t *gd, ulong dest_addr)
96 {
97 struct bd_info *bd;
98
99 bd = (struct bd_info *)(gd + sizeof(gd_t));
100 memset(bd, 0, sizeof(struct bd_info));
101 gd->bd = bd;
102
103 arch_cpu_init();
104 get_clocks();
105 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
106 CONFIG_SPL_RELOC_MALLOC_SIZE);
107 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
108
109 #ifdef CONFIG_SPL_NAND_BOOT
110 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
111 (uchar *)SPL_ENV_ADDR);
112 #endif
113 #ifdef CONFIG_SPL_MMC_BOOT
114 mmc_initialize(bd);
115 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
116 (uchar *)SPL_ENV_ADDR);
117 #endif
118 #ifdef CONFIG_SPL_SPI_BOOT
119 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
120 (uchar *)SPL_ENV_ADDR);
121 #endif
122
123 gd->env_addr = (ulong)(SPL_ENV_ADDR);
124 gd->env_valid = ENV_VALID;
125
126 i2c_init_all();
127
128 dram_init();
129
130 #ifdef CONFIG_SPL_MMC_BOOT
131 mmc_boot();
132 #elif defined(CONFIG_SPL_SPI_BOOT)
133 fsl_spi_boot();
134 #elif defined(CONFIG_SPL_NAND_BOOT)
135 nand_boot();
136 #endif
137 }
138