1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <clock_legacy.h>
7 #include <console.h>
8 #include <env_internal.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <ns16550.h>
12 #include <nand.h>
13 #include <i2c.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <spi_flash.h>
17 #include <asm/global_data.h>
18 #include "../common/sleep.h"
19 #include "../common/spl.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
get_effective_memsize(void)23 phys_size_t get_effective_memsize(void)
24 {
25 return CONFIG_SYS_L3_SIZE;
26 }
27
get_board_sys_clk(void)28 unsigned long get_board_sys_clk(void)
29 {
30 return CONFIG_SYS_CLK_FREQ;
31 }
32
33 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
board_init_f(ulong bootflag)34 void board_init_f(ulong bootflag)
35 {
36 u32 plat_ratio, sys_clk, uart_clk;
37 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
38 u32 porsr1, pinctl;
39 u32 svr = get_svr();
40 #endif
41 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
42
43 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
44 if (IS_SVR_REV(svr, 1, 0)) {
45 /*
46 * There is T1040 SoC issue where NOR, FPGA are inaccessible
47 * during NAND boot because IFC signals > IFC_AD7 are not
48 * enabled. This workaround changes RCW source to make all
49 * signals enabled.
50 */
51 porsr1 = in_be32(&gur->porsr1);
52 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
53 | 0x24800000);
54 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
55 pinctl);
56 }
57 #endif
58
59 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
60 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
61
62 /* Update GD pointer */
63 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
64
65 #ifdef CONFIG_DEEP_SLEEP
66 /* disable the console if boot from deep sleep */
67 if (is_warm_boot())
68 fsl_dp_disable_console();
69 #endif
70 /* compiler optimization barrier needed for GCC >= 3.4 */
71 __asm__ __volatile__("" : : : "memory");
72
73 console_init_f();
74
75 /* initialize selected port with appropriate baud rate */
76 sys_clk = get_board_sys_clk();
77 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
78 uart_clk = sys_clk * plat_ratio / 2;
79
80 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
81 uart_clk / 16 / CONFIG_BAUDRATE);
82
83 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
84 }
85
board_init_r(gd_t * gd,ulong dest_addr)86 void board_init_r(gd_t *gd, ulong dest_addr)
87 {
88 struct bd_info *bd;
89
90 bd = (struct bd_info *)(gd + sizeof(gd_t));
91 memset(bd, 0, sizeof(struct bd_info));
92 gd->bd = bd;
93
94 arch_cpu_init();
95 get_clocks();
96 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
97 CONFIG_SPL_RELOC_MALLOC_SIZE);
98 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
99
100 #ifdef CONFIG_SPL_MMC_BOOT
101 mmc_initialize(bd);
102 #endif
103
104 /* relocate environment function pointers etc. */
105 #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
106 defined(CONFIG_ENV_IS_IN_SPI_FLASH)
107 #ifdef CONFIG_SPL_NAND_BOOT
108 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
109 (uchar *)SPL_ENV_ADDR);
110 #endif
111 #ifdef CONFIG_SPL_MMC_BOOT
112 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
113 (uchar *)SPL_ENV_ADDR);
114 #endif
115 #ifdef CONFIG_SPL_SPI_BOOT
116 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
117 (uchar *)SPL_ENV_ADDR);
118 #endif
119 gd->env_addr = (ulong)(SPL_ENV_ADDR);
120 gd->env_valid = ENV_VALID;
121 #endif
122
123 i2c_init_all();
124
125 puts("\n\n");
126
127 dram_init();
128
129 #ifdef CONFIG_SPL_MMC_BOOT
130 mmc_boot();
131 #elif defined(CONFIG_SPL_SPI_BOOT)
132 fsl_spi_boot();
133 #elif defined(CONFIG_SPL_NAND_BOOT)
134 nand_boot();
135 #endif
136 }
137