1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * Authors: Nick.Spence@freescale.com
7 * Wilson.Lo@freescale.com
8 * scottwood@freescale.com
9 *
10 * This files is mostly identical to the original from
11 * board\freescale\mpc8315erdb\sdram.c
12 */
13
14 #ifndef CONFIG_MPC83XX_SDRAM
15
16 #include <common.h>
17 #include <init.h>
18 #include <mpc83xx.h>
19 #include <spd_sdram.h>
20
21 #include <asm/bitops.h>
22 #include <asm/global_data.h>
23 #include <asm/io.h>
24
25 #include <asm/processor.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 /* Fixed sdram init -- doesn't use serial presence detect.
30 *
31 * This is useful for faster booting in configs where the RAM is unlikely
32 * to be changed, or for things like NAND booting where space is tight.
33 */
fixed_sdram(void)34 static long fixed_sdram(void)
35 {
36 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
37 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
38 u32 msize_log2 = __ilog2(msize);
39
40 out_be32(&im->sysconf.ddrlaw[0].bar,
41 CONFIG_SYS_SDRAM_BASE & 0xfffff000);
42 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
43 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
44
45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
46 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
47
48 /* Currently we use only one CS, so disable the other bank. */
49 out_be32(&im->ddr.cs_config[1], 0);
50
51 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
52 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
53 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
54 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
55 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
56
57 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
58 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
59 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
60 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
61
62 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
63 sync();
64
65 /* enable DDR controller */
66 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
67 sync();
68
69 return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
70 }
71
dram_init(void)72 int dram_init(void)
73 {
74 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
75 u32 msize;
76
77 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
78 return -ENXIO;
79
80 /* DDR SDRAM */
81 msize = fixed_sdram();
82
83 /* return total bus SDRAM size(bytes) -- DDR */
84 gd->ram_size = msize;
85
86 return 0;
87 }
88
89 #endif /* !CONFIG_MPC83XX_SDRAM */
90