1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
5 */
6
7 #include <config.h>
8 #include <fdt_support.h>
9 #include <ide.h>
10 #include <init.h>
11 #include <net.h>
12 #include <netdev.h>
13 #include <pci.h>
14 #include <pci_gt64120.h>
15 #include <pci_msc01.h>
16 #include <rtc.h>
17 #include <asm/global_data.h>
18 #include <linux/delay.h>
19
20 #include <asm/addrspace.h>
21 #include <asm/io.h>
22 #include <asm/malta.h>
23
24 #include "superio.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define MALTA_GT_PATH "/pci0@1be00000"
29 #define MALTA_MSC_PATH "/pci0@1bd00000"
30
31 enum core_card {
32 CORE_UNKNOWN,
33 CORE_LV,
34 CORE_FPGA6,
35 };
36
37 enum sys_con {
38 SYSCON_UNKNOWN,
39 SYSCON_GT64120,
40 SYSCON_MSC01,
41 };
42
malta_lcd_puts(const char * str)43 static void malta_lcd_puts(const char *str)
44 {
45 int i;
46 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
47
48 /* print up to 8 characters of the string */
49 for (i = 0; i < min((int)strlen(str), 8); i++) {
50 __raw_writel(str[i], reg);
51 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
52 }
53
54 /* fill the rest of the display with spaces */
55 for (; i < 8; i++) {
56 __raw_writel(' ', reg);
57 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
58 }
59 }
60
malta_core_card(void)61 static enum core_card malta_core_card(void)
62 {
63 u32 corid, rev;
64 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
65
66 rev = __raw_readl(reg);
67 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
68
69 switch (corid) {
70 case MALTA_REVISION_CORID_CORE_LV:
71 return CORE_LV;
72
73 case MALTA_REVISION_CORID_CORE_FPGA6:
74 return CORE_FPGA6;
75
76 default:
77 return CORE_UNKNOWN;
78 }
79 }
80
malta_sys_con(void)81 static enum sys_con malta_sys_con(void)
82 {
83 switch (malta_core_card()) {
84 case CORE_LV:
85 return SYSCON_GT64120;
86
87 case CORE_FPGA6:
88 return SYSCON_MSC01;
89
90 default:
91 return SYSCON_UNKNOWN;
92 }
93 }
94
dram_init(void)95 int dram_init(void)
96 {
97 gd->ram_size = CONFIG_SYS_MEM_SIZE;
98
99 return 0;
100 }
101
checkboard(void)102 int checkboard(void)
103 {
104 enum core_card core;
105
106 malta_lcd_puts("U-Boot");
107 puts("Board: MIPS Malta");
108
109 core = malta_core_card();
110 switch (core) {
111 case CORE_LV:
112 puts(" CoreLV");
113 break;
114
115 case CORE_FPGA6:
116 puts(" CoreFPGA6");
117 break;
118
119 default:
120 puts(" CoreUnknown");
121 }
122
123 putc('\n');
124 return 0;
125 }
126
127 #if !IS_ENABLED(CONFIG_DM_ETH)
board_eth_init(struct bd_info * bis)128 int board_eth_init(struct bd_info *bis)
129 {
130 return pci_eth_init(bis);
131 }
132 #endif
133
_machine_restart(void)134 void _machine_restart(void)
135 {
136 void __iomem *reset_base;
137
138 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
139 __raw_writel(GORESET, reset_base);
140 mdelay(1000);
141 }
142
board_early_init_f(void)143 int board_early_init_f(void)
144 {
145 ulong io_base;
146
147 /* choose correct PCI I/O base */
148 switch (malta_sys_con()) {
149 case SYSCON_GT64120:
150 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
151 break;
152
153 case SYSCON_MSC01:
154 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
155 break;
156
157 default:
158 return -1;
159 }
160
161 set_io_port_base(io_base);
162
163 /* setup FDC37M817 super I/O controller */
164 malta_superio_init();
165
166 return 0;
167 }
168
misc_init_r(void)169 int misc_init_r(void)
170 {
171 rtc_reset();
172
173 return 0;
174 }
175
176 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
177 /*
178 * TODO: currently doesn't work because rw_fdt_blob points to a
179 * NOR flash address. This needs some changes in board_init_f.
180 */
board_fix_fdt(void * rw_fdt_blob)181 int board_fix_fdt(void *rw_fdt_blob)
182 {
183 int node = -1;
184
185 switch (malta_sys_con()) {
186 case SYSCON_GT64120:
187 node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
188 break;
189 default:
190 case SYSCON_MSC01:
191 node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
192 break;
193 }
194
195 return fdt_status_okay(rw_fdt_blob, node);
196 }
197 #endif
198
board_early_init_r(void)199 int board_early_init_r(void)
200 {
201 struct udevice *dev;
202 int ret;
203
204 pci_init();
205
206 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
207 PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
208 if (ret)
209 panic("Failed to find PIIX4 PCI bridge\n");
210
211 /* setup PCI interrupt routing */
212 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
213 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
214 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
215 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
216
217 /* mux SERIRQ onto SERIRQ pin */
218 dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
219 PCI_CFG_PIIX4_GENCFG_SERIRQ);
220
221 /* enable SERIRQ - Linux currently depends upon this */
222 dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
223 PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
224
225 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
226 PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
227 if (ret)
228 panic("Failed to find PIIX4 IDE controller\n");
229
230 /* enable bus master & IO access */
231 dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
232 PCI_COMMAND_MASTER | PCI_COMMAND_IO);
233
234 /* set latency */
235 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
236
237 /* enable IDE/ATA */
238 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
239 PCI_CFG_PIIX4_IDETIM_IDE);
240 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
241 PCI_CFG_PIIX4_IDETIM_IDE);
242
243 return 0;
244 }
245