1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
4 *
5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-ddr.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <errno.h>
19 #include <spl.h>
20 #include <linux/delay.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
ccgr_init(void)24 static void ccgr_init(void)
25 {
26 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
27
28 writel(0x00C03F3F, &ccm->CCGR0);
29 writel(0x0030FC03, &ccm->CCGR1);
30 writel(0x0FFFC000, &ccm->CCGR2);
31 writel(0x3FF00000, &ccm->CCGR3);
32 writel(0x00FFF300, &ccm->CCGR4);
33 writel(0x0F0000C3, &ccm->CCGR5);
34 writel(0x000003FF, &ccm->CCGR6);
35 }
36
37 /* DDR3 */
38 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
39 .dram_sdclk_0 = 0x00000030,
40 .dram_sdclk_1 = 0x00000030,
41 .dram_cas = 0x00000030,
42 .dram_ras = 0x00000030,
43 .dram_reset = 0x00000030,
44 .dram_sdcke0 = 0x00003000,
45 .dram_sdcke1 = 0x00003000,
46 .dram_sdba2 = 0x00000000,
47 .dram_sdodt0 = 0x00000030,
48 .dram_sdodt1 = 0x00000030,
49
50 .dram_sdqs0 = 0x00000018,
51 .dram_sdqs1 = 0x00000018,
52 .dram_sdqs2 = 0x00000018,
53 .dram_sdqs3 = 0x00000018,
54 .dram_sdqs4 = 0x00000018,
55 .dram_sdqs5 = 0x00000018,
56 .dram_sdqs6 = 0x00000018,
57 .dram_sdqs7 = 0x00000018,
58
59 .dram_dqm0 = 0x00000018,
60 .dram_dqm1 = 0x00000018,
61 .dram_dqm2 = 0x00000018,
62 .dram_dqm3 = 0x00000018,
63 .dram_dqm4 = 0x00000018,
64 .dram_dqm5 = 0x00000018,
65 .dram_dqm6 = 0x00000018,
66 .dram_dqm7 = 0x00000018,
67 };
68
69 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
70 .grp_ddr_type = 0x000c0000,
71 .grp_ddrmode_ctl = 0x00020000,
72 .grp_ddrpke = 0x00000000,
73 .grp_addds = 0x00000030,
74 .grp_ctlds = 0x00000030,
75 .grp_ddrmode = 0x00020000,
76 .grp_b0ds = 0x00000018,
77 .grp_b1ds = 0x00000018,
78 .grp_b2ds = 0x00000018,
79 .grp_b3ds = 0x00000018,
80 .grp_b4ds = 0x00000018,
81 .grp_b5ds = 0x00000018,
82 .grp_b6ds = 0x00000018,
83 .grp_b7ds = 0x00000018,
84 };
85
86 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
87 .p0_mpwldectrl0 = 0x001F001F,
88 .p0_mpwldectrl1 = 0x001F001F,
89 .p1_mpwldectrl0 = 0x001F001F,
90 .p1_mpwldectrl1 = 0x001F001F,
91 .p0_mpdgctrl0 = 0x43270338,
92 .p0_mpdgctrl1 = 0x03200314,
93 .p1_mpdgctrl0 = 0x431A032F,
94 .p1_mpdgctrl1 = 0x03200263,
95 .p0_mprddlctl = 0x4B434748,
96 .p1_mprddlctl = 0x4445404C,
97 .p0_mpwrdlctl = 0x38444542,
98 .p1_mpwrdlctl = 0x4935493A,
99 };
100
101 /* MT41K256M16 (4Gb density) */
102 static const struct mx6_ddr3_cfg mt41k256m16 = {
103 .mem_speed = 1600,
104 .density = 4,
105 .width = 16,
106 .banks = 8,
107 .rowaddr = 15,
108 .coladdr = 10,
109 .pagesz = 2,
110 .trcd = 1375,
111 .trcmin = 4875,
112 .trasmin = 3500,
113 };
114
115 #ifdef CONFIG_MX6_DDRCAL
spl_dram_print_cal(struct mx6_ddr_sysinfo const * sysinfo)116 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
117 {
118 struct mx6_mmdc_calibration calibration = {0};
119
120 mmdc_read_calibration(sysinfo, &calibration);
121
122 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
123 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
124 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
125 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
126 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
127 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
128 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
129 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
130 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
131 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
132 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
133 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
134 }
135
spl_dram_perform_cal(struct mx6_ddr_sysinfo const * sysinfo)136 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
137 {
138 int ret;
139
140 /* Perform DDR DRAM calibration */
141 udelay(100);
142 ret = mmdc_do_write_level_calibration(sysinfo);
143 if (ret) {
144 printf("DDR: Write level calibration error [%d]\n", ret);
145 return;
146 }
147
148 ret = mmdc_do_dqs_calibration(sysinfo);
149 if (ret) {
150 printf("DDR: DQS calibration error [%d]\n", ret);
151 return;
152 }
153
154 spl_dram_print_cal(sysinfo);
155 }
156 #endif /* CONFIG_MX6_DDRCAL */
157
spl_dram_init(void)158 static void spl_dram_init(void)
159 {
160 struct mx6_ddr_sysinfo sysinfo = {
161 /* width of data bus:0=16,1=32,2=64 */
162 .dsize = 2,
163 /* config for full 4GB range so that get_mem_size() works */
164 .cs_density = 32, /* 32Gb per CS */
165 /* single chip select */
166 .ncs = 1,
167 .cs1_mirror = 0,
168 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
169 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
170 .walat = 1, /* Write additional latency */
171 .ralat = 5, /* Read additional latency */
172 .mif3_mode = 3, /* Command prediction working mode */
173 .bi_on = 1, /* Bank interleaving enabled */
174 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
175 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
176 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
177 .ddr_type = DDR_TYPE_DDR3,
178 .refsel = 1, /* Refresh cycles at 32KHz */
179 .refr = 7, /* 8 refresh commands per refresh cycle */
180 };
181
182 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
183 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
184
185 #ifdef CONFIG_MX6_DDRCAL
186 spl_dram_perform_cal(&sysinfo);
187 #endif
188 }
189
board_boot_order(u32 * spl_boot_list)190 void board_boot_order(u32 *spl_boot_list)
191 {
192 u32 boot_device = spl_boot_device();
193 u32 reg = imx6_src_get_boot_mode();
194
195 reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
196
197 debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
198 if (boot_device == BOOT_DEVICE_MMC1)
199 if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
200 boot_device = BOOT_DEVICE_MMC2;
201
202 spl_boot_list[0] = boot_device;
203 /*
204 * Below boot device is a 'fallback' - it shall always be possible to
205 * boot from SD card
206 */
207 spl_boot_list[1] = BOOT_DEVICE_MMC1;
208 }
209
board_init_f(ulong dummy)210 void board_init_f(ulong dummy)
211 {
212 /* setup AIPS and disable watchdog */
213 arch_cpu_init();
214
215 ccgr_init();
216 gpr_init();
217
218 /* setup GP timer */
219 timer_init();
220
221 /* Early - pre reloc - driver model setup */
222 spl_early_init();
223
224 /* UART clocks enabled and gd valid - init serial console */
225 preloader_console_init();
226
227 /* DDR initialization */
228 spl_dram_init();
229
230 /* Clear the BSS. */
231 memset(__bss_start, 0, __bss_end - __bss_start);
232 }
233