1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <asm/global_data.h>
5 #include <asm/io.h>
6 #include <fsl_ddr_sdram.h>
7
8 DECLARE_GLOBAL_DATA_PTR;
9
10 #define DCFG_GPPORCR1 0x20
11
12 #define GPPORCR1_MEM_MASK (0x7 << 5)
13 #define GPPORCR1_MEM_512MB_CS0 (0x0 << 5)
14 #define GPPORCR1_MEM_1GB_CS0 (0x1 << 5)
15 #define GPPORCR1_MEM_2GB_CS0 (0x2 << 5)
16 #define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5)
17 #define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5)
18 #define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5)
19 #define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5)
20
21 static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
22 .cs[0].bnds = 0x0000007f,
23 .cs[0].config = 0x80044402,
24 .cs[1].bnds = 0x008000ff,
25 .cs[1].config = 0x80004402,
26
27 .timing_cfg_0 = 0x9011010c,
28 .timing_cfg_3 = 0x010c1000,
29 .timing_cfg_1 = 0xbcb48c66,
30 .timing_cfg_2 = 0x0fc0d118,
31 .ddr_sdram_cfg = 0xe70c000c,
32 .ddr_sdram_cfg_2 = 0x24401111,
33 .ddr_sdram_mode = 0x00441c70,
34 .ddr_sdram_mode_3 = 0x00001c70,
35 .ddr_sdram_mode_5 = 0x00001c70,
36 .ddr_sdram_mode_7 = 0x00001c70,
37 .ddr_sdram_mode_2 = 0x00180000,
38 .ddr_sdram_mode_4 = 0x00180000,
39 .ddr_sdram_mode_6 = 0x00180000,
40 .ddr_sdram_mode_8 = 0x00180000,
41
42 .ddr_sdram_interval = 0x0c30030c,
43 .ddr_data_init = 0xdeadbeef,
44
45 .ddr_sdram_clk_cntl = 0x02400000,
46
47 .timing_cfg_4 = 0x00000001,
48 .timing_cfg_5 = 0x04401400,
49
50 .ddr_zq_cntl = 0x89080600,
51 .ddr_wrlvl_cntl = 0x8675f606,
52 .ddr_wrlvl_cntl_2 = 0x04080700,
53 .ddr_wrlvl_cntl_3 = 0x00000009,
54
55 .ddr_cdr1 = 0x80040000,
56 .ddr_cdr2 = 0x0000bc01,
57 };
58
fsl_initdram(void)59 int fsl_initdram(void)
60 {
61 u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
62 phys_size_t dram_size;
63
64 switch (gpporcr1 & GPPORCR1_MEM_MASK) {
65 case GPPORCR1_MEM_2GB_CS0:
66 dram_size = 0x80000000;
67 ddr_cfg_regs.cs[1].bnds = 0;
68 ddr_cfg_regs.cs[1].config = 0;
69 ddr_cfg_regs.cs[1].config_2 = 0;
70 break;
71 case GPPORCR1_MEM_4GB_CS0_1:
72 dram_size = 0x100000000ULL;
73 break;
74 case GPPORCR1_MEM_512MB_CS0:
75 dram_size = 0x20000000;
76 fallthrough; /* for now */
77 case GPPORCR1_MEM_1GB_CS0:
78 dram_size = 0x40000000;
79 fallthrough; /* for now */
80 case GPPORCR1_MEM_4GB_CS0_2:
81 dram_size = 0x100000000ULL;
82 fallthrough; /* for now */
83 case GPPORCR1_MEM_8GB_CS0_1:
84 case GPPORCR1_MEM_8GB_CS0_1_2_3:
85 dram_size = 0x200000000ULL;
86 fallthrough; /* for now */
87 default:
88 panic("Unsupported memory configuration (%08x)\n",
89 gpporcr1 & GPPORCR1_MEM_MASK);
90 break;
91 }
92
93 if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
94 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
95
96 gd->ram_size = dram_size;
97
98 return 0;
99 }
100