1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Logic PD, Inc.
4 *
5 * Author: Adam Ford <aford173@gmail.com>
6 *
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
9 */
10
11 #include <common.h>
12 #include <env.h>
13 #include <init.h>
14 #include <miiphy.h>
15 #include <input.h>
16 #include <mmc.h>
17 #include <fsl_esdhc_imx.h>
18 #include <serial.h>
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <linux/sizes.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/arch/iomux.h>
26 #include <asm/arch/mxc_hdmi.h>
27 #include <asm/arch/mx6-pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/mach-imx/boot_mode.h>
30 #include <asm/mach-imx/iomux-v3.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41
dram_init(void)42 int dram_init(void)
43 {
44 gd->ram_size = imx_ddr_size();
45 return 0;
46 }
47
48 static iomux_v3_cfg_t const nand_pads[] = {
49 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
50 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
51 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
52 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
53 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
54 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
55 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
56 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
57 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
58 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
59 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
60 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
61 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
62 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
63 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
64 };
65
setup_nand_pins(void)66 static void setup_nand_pins(void)
67 {
68 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
69 }
70
ar8031_phy_fixup(struct phy_device * phydev)71 static int ar8031_phy_fixup(struct phy_device *phydev)
72 {
73 unsigned short val;
74
75 /* To enable AR8031 output a 125MHz clk from CLK_25M */
76 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
77 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
78 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
79
80 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
81 val &= 0xffe3;
82 val |= 0x18;
83 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
84
85 /* introduce tx clock delay */
86 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
87 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
88 val |= 0x0100;
89 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
90
91 return 0;
92 }
93
board_phy_config(struct phy_device * phydev)94 int board_phy_config(struct phy_device *phydev)
95 {
96 ar8031_phy_fixup(phydev);
97
98 if (phydev->drv->config)
99 phydev->drv->config(phydev);
100
101 return 0;
102 }
103
104 /*
105 * Do not overwrite the console
106 * Use always serial for U-Boot console
107 */
overwrite_console(void)108 int overwrite_console(void)
109 {
110 return 1;
111 }
112
board_early_init_f(void)113 int board_early_init_f(void)
114 {
115 setup_nand_pins();
116 return 0;
117 }
118
board_init(void)119 int board_init(void)
120 {
121 /* address of boot parameters */
122 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
123 return 0;
124 }
125
board_late_init(void)126 int board_late_init(void)
127 {
128 env_set("board_name", "imx6logic");
129
130 if (is_mx6dq()) {
131 env_set("board_rev", "MX6DQ");
132 if (!env_get("fdt_file"))
133 env_set("fdt_file", "imx6q-logicpd.dtb");
134 }
135
136 return 0;
137 }
138
139 #ifdef CONFIG_SPL_BUILD
140 #include <asm/arch/mx6-ddr.h>
141 #include <asm/arch/mx6q-ddr.h>
142 #include <spl.h>
143 #include <linux/libfdt.h>
144
145 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)146 int spl_start_uboot(void)
147 {
148 /* break into full u-boot on 'c' */
149 if (serial_tstc() && serial_getc() == 'c')
150 return 1;
151
152 return 0;
153 }
154 #endif
155
board_boot_order(u32 * spl_boot_list)156 void board_boot_order(u32 *spl_boot_list)
157 {
158 struct src *psrc = (struct src *)SRC_BASE_ADDR;
159 unsigned int reg = readl(&psrc->sbmr1) >> 11;
160 u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
161 unsigned int bmode = readl(&src_base->sbmr2);
162
163 /* If bmode is serial or USB phy is active, return serial */
164 if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
165 spl_boot_list[0] = BOOT_DEVICE_BOARD;
166 return;
167 }
168
169 switch (boot_mode >> IMX6_BMODE_SHIFT) {
170 case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
171 spl_boot_list[0] = BOOT_DEVICE_NAND;
172 break;
173 case IMX6_BMODE_SD:
174 case IMX6_BMODE_ESD:
175 case IMX6_BMODE_MMC:
176 case IMX6_BMODE_EMMC:
177 /*
178 * Upon reading BOOT_CFG register the following map is done:
179 * Bit 11 and 12 of BOOT_CFG register can determine the current
180 * mmc port
181 * 0x1 SD1-SOM
182 * 0x2 SD2-Baseboard
183 */
184
185 reg &= 0x3; /* Only care about bottom 2 bits */
186 switch (reg) {
187 case 0:
188 spl_boot_list[0] = BOOT_DEVICE_MMC1;
189 break;
190 case 1:
191 spl_boot_list[0] = BOOT_DEVICE_MMC2;
192 break;
193 }
194 break;
195 default:
196 /* By default use USB downloader */
197 spl_boot_list[0] = BOOT_DEVICE_BOARD;
198 break;
199 }
200
201 /* As a last resort, use serial downloader */
202 spl_boot_list[1] = BOOT_DEVICE_BOARD;
203 }
204
ccgr_init(void)205 static void ccgr_init(void)
206 {
207 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
208
209 writel(0x00C03F3F, &ccm->CCGR0);
210 writel(0x0030FC03, &ccm->CCGR1);
211 writel(0x0FFFC000, &ccm->CCGR2);
212 writel(0x3FF00000, &ccm->CCGR3);
213 writel(0xFFFFF300, &ccm->CCGR4);
214 writel(0x0F0000F3, &ccm->CCGR5);
215 writel(0x00000FFF, &ccm->CCGR6);
216 }
217
218 static int mx6q_dcd_table[] = {
219 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
220 MX6_IOM_GRP_DDRPKE, 0x00000000,
221 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
222 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
223 MX6_IOM_DRAM_CAS, 0x00000030,
224 MX6_IOM_DRAM_RAS, 0x00000030,
225 MX6_IOM_GRP_ADDDS, 0x00000030,
226 MX6_IOM_DRAM_RESET, 0x00000030,
227 MX6_IOM_DRAM_SDBA2, 0x00000000,
228 MX6_IOM_DRAM_SDODT0, 0x00000030,
229 MX6_IOM_DRAM_SDODT1, 0x00000030,
230 MX6_IOM_GRP_CTLDS, 0x00000030,
231 MX6_IOM_DDRMODE_CTL, 0x00020000,
232 MX6_IOM_DRAM_SDQS0, 0x00000030,
233 MX6_IOM_DRAM_SDQS1, 0x00000030,
234 MX6_IOM_DRAM_SDQS2, 0x00000030,
235 MX6_IOM_DRAM_SDQS3, 0x00000030,
236 MX6_IOM_GRP_DDRMODE, 0x00020000,
237 MX6_IOM_GRP_B0DS, 0x00000030,
238 MX6_IOM_GRP_B1DS, 0x00000030,
239 MX6_IOM_GRP_B2DS, 0x00000030,
240 MX6_IOM_GRP_B3DS, 0x00000030,
241 MX6_IOM_DRAM_DQM0, 0x00000030,
242 MX6_IOM_DRAM_DQM1, 0x00000030,
243 MX6_IOM_DRAM_DQM2, 0x00000030,
244 MX6_IOM_DRAM_DQM3, 0x00000030,
245 MX6_MMDC_P0_MDSCR, 0x00008000,
246 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
247 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
248 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
249 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
250 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
251 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
252 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
253 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
254 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
255 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
256 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
257 MX6_MMDC_P0_MPMUR0, 0x00000800,
258 MX6_MMDC_P0_MDPDC, 0x00020036,
259 MX6_MMDC_P0_MDOTC, 0x09444040,
260 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
261 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
262 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
263 MX6_MMDC_P0_MDMISC, 0x00011740,
264 MX6_MMDC_P0_MDSCR, 0x00008000,
265 MX6_MMDC_P0_MDRWD, 0x000026D2,
266 MX6_MMDC_P0_MDOR, 0x00BE1023,
267 MX6_MMDC_P0_MDASP, 0x00000047,
268 MX6_MMDC_P0_MDCTL, 0x85190000,
269 MX6_MMDC_P0_MDSCR, 0x00888032,
270 MX6_MMDC_P0_MDSCR, 0x00008033,
271 MX6_MMDC_P0_MDSCR, 0x00008031,
272 MX6_MMDC_P0_MDSCR, 0x19408030,
273 MX6_MMDC_P0_MDSCR, 0x04008040,
274 MX6_MMDC_P0_MDREF, 0x00007800,
275 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
276 MX6_MMDC_P0_MDPDC, 0x00025576,
277 MX6_MMDC_P0_MAPSR, 0x00011006,
278 MX6_MMDC_P0_MDSCR, 0x00000000,
279 /* enable AXI cache for VDOA/VPU/IPU */
280
281 MX6_IOMUXC_GPR4, 0xF00000CF,
282 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
283 MX6_IOMUXC_GPR6, 0x007F007F,
284 MX6_IOMUXC_GPR7, 0x007F007F,
285 };
286
ddr_init(int * table,int size)287 static void ddr_init(int *table, int size)
288 {
289 int i;
290
291 for (i = 0; i < size / 2 ; i++)
292 writel(table[2 * i + 1], table[2 * i]);
293 }
294
spl_dram_init(void)295 static void spl_dram_init(void)
296 {
297 if (is_mx6dq())
298 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
299 }
300
board_init_f(ulong dummy)301 void board_init_f(ulong dummy)
302 {
303 /* DDR initialization */
304 spl_dram_init();
305
306 /* setup AIPS and disable watchdog */
307 arch_cpu_init();
308
309 ccgr_init();
310 gpr_init();
311
312 /* iomux and setup of uart and NAND pins */
313 board_early_init_f();
314
315 /* setup GP timer */
316 timer_init();
317
318 /* Enable device tree and early DM support*/
319 spl_early_init();
320
321 /* UART clocks enabled and gd valid - init serial console */
322 preloader_console_init();
323 }
324 #endif
325