1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2018 Microsemi Corporation
4  */
5 
6 #include <common.h>
7 #include <image.h>
8 #include <init.h>
9 #include <asm/io.h>
10 #include <led.h>
11 #include <miiphy.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <asm/global_data.h>
15 
16 enum {
17 	BOARD_TYPE_PCB110 = 0xAABBCE00,
18 	BOARD_TYPE_PCB111,
19 	BOARD_TYPE_PCB112,
20 };
21 
board_early_init_r(void)22 int board_early_init_r(void)
23 {
24 	/* Prepare SPI controller to be used in master mode */
25 	writel(0, BASE_CFG + ICPU_SW_MODE);
26 	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
27 			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
28 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
29 
30 	/* Address of boot parameters */
31 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
32 
33 	/* LED setup */
34 	if (IS_ENABLED(CONFIG_LED))
35 		led_default_state();
36 
37 	return 0;
38 }
39 
vcoreiii_gpio_set_alternate(int gpio,int mode)40 static void vcoreiii_gpio_set_alternate(int gpio, int mode)
41 {
42 	u32 mask;
43 	u32 val0, val1;
44 	void __iomem *reg0, *reg1;
45 
46 	if (gpio < 32) {
47 		mask = BIT(gpio);
48 		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
49 		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
50 	} else {
51 		gpio -= 32;
52 		mask = BIT(gpio);
53 		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
54 		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
55 	}
56 	val0 = readl(reg0);
57 	val1 = readl(reg1);
58 	if (mode == 1) {
59 		writel(val0 | mask, reg0);
60 		writel(val1 & ~mask, reg1);
61 	} else if (mode == 2) {
62 		writel(val0 & ~mask, reg0);
63 		writel(val1 | mask, reg1);
64 	} else if (mode == 3) {
65 		writel(val0 | mask, reg0);
66 		writel(val1 | mask, reg1);
67 	} else {
68 		writel(val0 & ~mask, reg0);
69 		writel(val1 & ~mask, reg1);
70 	}
71 }
72 
board_phy_config(struct phy_device * phydev)73 int board_phy_config(struct phy_device *phydev)
74 {
75 	if (gd->board_type == BOARD_TYPE_PCB110 ||
76 	    gd->board_type == BOARD_TYPE_PCB112) {
77 		phy_write(phydev, 0, 31, 0x10);
78 		phy_write(phydev, 0, 18, 0x80F0);
79 		while (phy_read(phydev, 0, 18) & 0x8000)
80 			;
81 		phy_write(phydev, 0, 31, 0);
82 	}
83 	if (gd->board_type == BOARD_TYPE_PCB111) {
84 		phy_write(phydev, 0, 31, 0x10);
85 		phy_write(phydev, 0, 18, 0x80A0);
86 		while (phy_read(phydev, 0, 18) & 0x8000)
87 			;
88 		phy_write(phydev, 0, 14, 0x800);
89 		phy_write(phydev, 0, 31, 0);
90 	}
91 
92 	return 0;
93 }
94 
board_debug_uart_init(void)95 void board_debug_uart_init(void)
96 {
97 	/* too early for the pinctrl driver, so configure the UART pins here */
98 	vcoreiii_gpio_set_alternate(10, 1);
99 	vcoreiii_gpio_set_alternate(11, 1);
100 }
101 
do_board_detect(void)102 static void do_board_detect(void)
103 {
104 	int i;
105 	u16 pval;
106 
107 	/* MIIM 1 + 2  MDC/MDIO */
108 	for (i = 56; i < 60; i++)
109 		vcoreiii_gpio_set_alternate(i, 1);
110 
111 	/* small delay for settling the pins */
112 	mdelay(30);
113 
114 	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
115 	    ((pval >> 4) & 0x3F) == 0x3c) {
116 		gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
117 	} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
118 		   ((pval >> 4) & 0x3F) == 0x3c) {
119 		gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
120 	} else {
121 		/* Fall-back */
122 		gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
123 	}
124 }
125 
126 #if defined(CONFIG_MULTI_DTB_FIT)
board_fit_config_name_match(const char * name)127 int board_fit_config_name_match(const char *name)
128 {
129 	if (gd->board_type == BOARD_TYPE_PCB110 &&
130 	    strcmp(name, "jr2_pcb110") == 0)
131 		return 0;
132 
133 	if (gd->board_type == BOARD_TYPE_PCB111 &&
134 	    strcmp(name, "jr2_pcb111") == 0)
135 		return 0;
136 
137 	if (gd->board_type == BOARD_TYPE_PCB112 &&
138 	    strcmp(name, "serval2_pcb112") == 0)
139 		return 0;
140 
141 	return -1;
142 }
143 #endif
144 
145 #if defined(CONFIG_DTB_RESELECT)
embedded_dtb_select(void)146 int embedded_dtb_select(void)
147 {
148 	do_board_detect();
149 	fdtdec_setup();
150 
151 	return 0;
152 }
153 #endif
154