1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <log.h>
9 #include <asm/io.h>
10 #include <asm/arch-tegra/tegra_i2c.h>
11 #include <linux/delay.h>
12 #include "as3722_init.h"
13
14 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
15
tegra_i2c_ll_write_addr(uint addr,uint config)16 void tegra_i2c_ll_write_addr(uint addr, uint config)
17 {
18 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
19
20 writel(addr, ®->cmd_addr0);
21 writel(config, ®->cnfg);
22 }
23
tegra_i2c_ll_write_data(uint data,uint config)24 void tegra_i2c_ll_write_data(uint data, uint config)
25 {
26 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
27
28 writel(data, ®->cmd_data1);
29 writel(config, ®->cnfg);
30 }
31
pmic_enable_cpu_vdd(void)32 void pmic_enable_cpu_vdd(void)
33 {
34 debug("%s entry\n", __func__);
35
36 #ifdef AS3722_SD1VOLTAGE_DATA
37 /* Set up VDD_CORE, for boards where OTP is incorrect*/
38 debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
39 /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
40 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
41 tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
42 /*
43 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
44 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
45 */
46 udelay(10 * 1000);
47 #endif
48
49 debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
50 /*
51 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
52 * First set VDD to 1.0V, then enable the VDD regulator.
53 */
54 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
55 tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
56 /*
57 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
58 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
59 */
60 udelay(10 * 1000);
61
62 debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
63 /*
64 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
65 * First set VDD to 1.0V, then enable the VDD regulator.
66 */
67 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
68 tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
69 /*
70 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
71 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
72 */
73 udelay(10 * 1000);
74
75 debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
76 /*
77 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
78 * First set VDD to 1.2V, then enable the VDD regulator.
79 */
80 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
81 tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
82 /*
83 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
84 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
85 */
86 udelay(10 * 1000);
87
88 debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
89 /*
90 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
91 * First set it to bypass 3.3V straight thru, then enable the regulator
92 *
93 * NOTE: We do this early because doing it later seems to hose the CPU
94 * power rail/partition startup. Need to debug.
95 */
96 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
97 tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
98 /*
99 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
100 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
101 */
102 udelay(10 * 1000);
103 }
104