1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board/renesas/falcon/falcon.c
4  *     This file is Falcon board support.
5  *
6  * Copyright (C) 2020 Renesas Electronics Corp.
7  */
8 
9 #include <common.h>
10 #include <asm/arch/rmobile.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <asm/mach-types.h>
15 #include <asm/processor.h>
16 #include <linux/errno.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 #define CPGWPR		0xE6150000
21 #define CPGWPCR		0xE6150004
22 
23 #define EXTAL_CLK	16666600u
24 #define CNTCR_BASE	0xE6080000
25 #define CNTFID0		(CNTCR_BASE + 0x020)
26 #define CNTCR_EN	BIT(0)
27 
init_generic_timer(void)28 static void init_generic_timer(void)
29 {
30 	u32 freq;
31 
32 	/* Set frequency data in CNTFID0 */
33 	freq = EXTAL_CLK;
34 
35 	/* Update memory mapped and register based freqency */
36 	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
37 	writel(freq, CNTFID0);
38 
39 	/* Enable counter */
40 	setbits_le32(CNTCR_BASE, CNTCR_EN);
41 }
42 
43 /* Distributor Registers */
44 #define GICD_BASE	0xF1000000
45 
46 /* ReDistributor Registers for Control and Physical LPIs */
47 #define GICR_LPI_BASE	0xF1060000
48 #define GICR_WAKER	0x0014
49 #define GICR_PWRR	0x0024
50 #define GICR_LPI_WAKER	(GICR_LPI_BASE + GICR_WAKER)
51 #define GICR_LPI_PWRR	(GICR_LPI_BASE + GICR_PWRR)
52 
53 /* ReDistributor Registers for SGIs and PPIs */
54 #define GICR_SGI_BASE	0xF1070000
55 #define GICR_IGROUPR0	0x0080
56 
init_gic_v3(void)57 static void init_gic_v3(void)
58 {
59 	 /* GIC v3 power on */
60 	writel(0x00000002, (GICR_LPI_PWRR));
61 
62 	/* Wait till the WAKER_CA_BIT changes to 0 */
63 	writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
64 	while (readl(GICR_LPI_WAKER) & 0x00000004)
65 		;
66 
67 	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
68 }
69 
s_init(void)70 void s_init(void)
71 {
72 	init_generic_timer();
73 }
74 
board_early_init_f(void)75 int board_early_init_f(void)
76 {
77 	/* Unlock CPG access */
78 	writel(0x5A5AFFFF, CPGWPR);
79 	writel(0xA5A50000, CPGWPCR);
80 
81 	return 0;
82 }
83 
board_init(void)84 int board_init(void)
85 {
86 	/* address of boot parameters */
87 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
88 
89 	init_gic_v3();
90 
91 	return 0;
92 }
93 
94 #define RST_BASE	0xE6160000 /* Domain0 */
95 #define RST_SRESCR0	(RST_BASE + 0x18)
96 #define RST_SPRES	0x5AA58000
97 
reset_cpu(void)98 void reset_cpu(void)
99 {
100 	writel(RST_SPRES, RST_SRESCR0);
101 }
102