1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/gose/gose.c
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <env.h>
11 #include <hang.h>
12 #include <init.h>
13 #include <malloc.h>
14 #include <dm.h>
15 #include <asm/global_data.h>
16 #include <dm/platform_data/serial_sh.h>
17 #include <env_internal.h>
18 #include <asm/processor.h>
19 #include <asm/mach-types.h>
20 #include <asm/io.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/rmobile.h>
27 #include <asm/arch/rcar-mstp.h>
28 #include <asm/arch/sh_sdhi.h>
29 #include <netdev.h>
30 #include <miiphy.h>
31 #include <i2c.h>
32 #include "qos.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)37 void s_init(void)
38 {
39 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
40 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
41 u32 stc;
42
43 /* Watchdog init */
44 writel(0xA5A5A500, &rwdt->rwtcsra);
45 writel(0xA5A5A500, &swdt->swtcsra);
46
47 /* CPU frequency setting. Set to 1.5GHz */
48 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
49 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
50
51 /* QoS */
52 qos_init();
53 }
54
55 #define TMU0_MSTP125 BIT(25)
56
57 #define SD1CKCR 0xE6150078
58 #define SD2CKCR 0xE615026C
59 #define SD_97500KHZ 0x7
60
board_early_init_f(void)61 int board_early_init_f(void)
62 {
63 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
64
65 /*
66 * SD0 clock is set to 97.5MHz by default.
67 * Set SD1 and SD2 to the 97.5MHz as well.
68 */
69 writel(SD_97500KHZ, SD1CKCR);
70 writel(SD_97500KHZ, SD2CKCR);
71
72 return 0;
73 }
74
75 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
76
board_init(void)77 int board_init(void)
78 {
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
81
82 /* Force ethernet PHY out of reset */
83 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
84 gpio_direction_output(ETHERNET_PHY_RESET, 0);
85 mdelay(10);
86 gpio_direction_output(ETHERNET_PHY_RESET, 1);
87
88 return 0;
89 }
90
dram_init(void)91 int dram_init(void)
92 {
93 if (fdtdec_setup_mem_size_base() != 0)
94 return -EINVAL;
95
96 return 0;
97 }
98
dram_init_banksize(void)99 int dram_init_banksize(void)
100 {
101 fdtdec_setup_memory_banksize();
102
103 return 0;
104 }
105
106 /* KSZ8041RNLI */
107 #define PHY_CONTROL1 0x1E
108 #define PHY_LED_MODE 0xC000
109 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)110 int board_phy_config(struct phy_device *phydev)
111 {
112 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
113 ret &= ~PHY_LED_MODE;
114 ret |= PHY_LED_MODE_ACK;
115 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
116
117 return 0;
118 }
119
reset_cpu(void)120 void reset_cpu(void)
121 {
122 struct udevice *dev;
123 const u8 pmic_bus = 6;
124 const u8 pmic_addr = 0x58;
125 u8 data;
126 int ret;
127
128 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
129 if (ret)
130 hang();
131
132 ret = dm_i2c_read(dev, 0x13, &data, 1);
133 if (ret)
134 hang();
135
136 data |= BIT(1);
137
138 ret = dm_i2c_write(dev, 0x13, &data, 1);
139 if (ret)
140 hang();
141 }
142
env_get_location(enum env_operation op,int prio)143 enum env_location env_get_location(enum env_operation op, int prio)
144 {
145 const u32 load_magic = 0xb33fc0de;
146
147 /* Block environment access if loaded using JTAG */
148 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
149 (op != ENVOP_INIT))
150 return ENVL_UNKNOWN;
151
152 if (prio)
153 return ENVL_UNKNOWN;
154
155 return ENVL_SPI_FLASH;
156 }
157