1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/silk/silk.c
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <env.h>
12 #include <hang.h>
13 #include <init.h>
14 #include <malloc.h>
15 #include <dm.h>
16 #include <asm/global_data.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include <env_internal.h>
19 #include <asm/processor.h>
20 #include <asm/mach-types.h>
21 #include <asm/io.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/gpio.h>
27 #include <asm/arch/rmobile.h>
28 #include <asm/arch/rcar-mstp.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/sh_sdhi.h>
31 #include <netdev.h>
32 #include <miiphy.h>
33 #include <i2c.h>
34 #include <div64.h>
35 #include "qos.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
s_init(void)39 void s_init(void)
40 {
41 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
42 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
43
44 /* Watchdog init */
45 writel(0xA5A5A500, &rwdt->rwtcsra);
46 writel(0xA5A5A500, &swdt->swtcsra);
47
48 /* QoS */
49 qos_init();
50 }
51
52 #define TMU0_MSTP125 BIT(25)
53 #define MMC0_MSTP315 BIT(15)
54
55 #define SD1CKCR 0xE6150078
56 #define SD_97500KHZ 0x7
57
board_early_init_f(void)58 int board_early_init_f(void)
59 {
60 /* TMU */
61 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
62
63 /* Set SD1 to the 97.5MHz */
64 writel(SD_97500KHZ, SD1CKCR);
65
66 return 0;
67 }
68
69 #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
70
board_init(void)71 int board_init(void)
72 {
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
75
76 /* Force ethernet PHY out of reset */
77 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
78 gpio_direction_output(ETHERNET_PHY_RESET, 0);
79 mdelay(20);
80 gpio_direction_output(ETHERNET_PHY_RESET, 1);
81 udelay(1);
82
83 return 0;
84 }
85
dram_init(void)86 int dram_init(void)
87 {
88 if (fdtdec_setup_mem_size_base() != 0)
89 return -EINVAL;
90
91 return 0;
92 }
93
dram_init_banksize(void)94 int dram_init_banksize(void)
95 {
96 fdtdec_setup_memory_banksize();
97
98 return 0;
99 }
100
101 /* porter has KSZ8041RNLI */
102 #define PHY_CONTROL1 0x1E
103 #define PHY_LED_MODE 0xC000
104 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)105 int board_phy_config(struct phy_device *phydev)
106 {
107 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
108 ret &= ~PHY_LED_MODE;
109 ret |= PHY_LED_MODE_ACK;
110 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
111
112 return 0;
113 }
114
reset_cpu(void)115 void reset_cpu(void)
116 {
117 struct udevice *dev;
118 const u8 pmic_bus = 1;
119 const u8 pmic_addr = 0x5a;
120 u8 data;
121 int ret;
122
123 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
124 if (ret)
125 hang();
126
127 ret = dm_i2c_read(dev, 0x13, &data, 1);
128 if (ret)
129 hang();
130
131 data |= BIT(1);
132
133 ret = dm_i2c_write(dev, 0x13, &data, 1);
134 if (ret)
135 hang();
136 }
137
env_get_location(enum env_operation op,int prio)138 enum env_location env_get_location(enum env_operation op, int prio)
139 {
140 const u32 load_magic = 0xb33fc0de;
141
142 /* Block environment access if loaded using JTAG */
143 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
144 (op != ENVOP_INIT))
145 return ENVL_UNKNOWN;
146
147 if (prio)
148 return ENVL_UNKNOWN;
149
150 return ENVL_SPI_FLASH;
151 }
152