1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout.c
4 * This file is Stout board support.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
9 */
10
11 #include <common.h>
12 #include <env.h>
13 #include <init.h>
14 #include <malloc.h>
15 #include <netdev.h>
16 #include <dm.h>
17 #include <asm/global_data.h>
18 #include <dm/platform_data/serial_sh.h>
19 #include <env_internal.h>
20 #include <asm/processor.h>
21 #include <asm/mach-types.h>
22 #include <asm/io.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/gpio.h>
28 #include <asm/arch/rmobile.h>
29 #include <asm/arch/rcar-mstp.h>
30 #include <asm/arch/mmc.h>
31 #include <asm/arch/sh_sdhi.h>
32 #include <miiphy.h>
33 #include <i2c.h>
34 #include <mmc.h>
35 #include "qos.h"
36 #include "cpld.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)41 void s_init(void)
42 {
43 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
44 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
45
46 /* Watchdog init */
47 writel(0xA5A5A500, &rwdt->rwtcsra);
48 writel(0xA5A5A500, &swdt->swtcsra);
49
50 /* CPU frequency setting. Set to 1.4GHz */
51 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
52 u32 stat = 0;
53 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
54 << PLL0_STC_BIT;
55 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
56
57 do {
58 stat = readl(PLLECR) & PLL0ST;
59 } while (stat == 0x0);
60 }
61
62 /* QoS(Quality-of-Service) Init */
63 qos_init();
64 }
65
66 #define TMU0_MSTP125 BIT(25)
67
68 #define SD2CKCR 0xE6150078
69 #define SD2_97500KHZ 0x7
70
board_early_init_f(void)71 int board_early_init_f(void)
72 {
73 /* TMU0 */
74 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
75
76 /*
77 * SD0 clock is set to 97.5MHz by default.
78 * Set SD2 to the 97.5MHz as well.
79 */
80 writel(SD2_97500KHZ, SD2CKCR);
81
82 return 0;
83 }
84
85 #define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
86
board_init(void)87 int board_init(void)
88 {
89 /* adress of boot parameters */
90 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
91
92 cpld_init();
93
94 /* Force ethernet PHY out of reset */
95 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
96 gpio_direction_output(ETHERNET_PHY_RESET, 0);
97 mdelay(20);
98 gpio_direction_output(ETHERNET_PHY_RESET, 1);
99
100 return 0;
101 }
102
dram_init(void)103 int dram_init(void)
104 {
105 if (fdtdec_setup_mem_size_base() != 0)
106 return -EINVAL;
107
108 return 0;
109 }
110
dram_init_banksize(void)111 int dram_init_banksize(void)
112 {
113 fdtdec_setup_memory_banksize();
114
115 return 0;
116 }
117
118 /* Stout has KSZ8041NL/RNL */
119 #define PHY_CONTROL1 0x1E
120 #define PHY_LED_MODE 0xC000
121 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)122 int board_phy_config(struct phy_device *phydev)
123 {
124 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
125 ret &= ~PHY_LED_MODE;
126 ret |= PHY_LED_MODE_ACK;
127 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
128
129 return 0;
130 }
131
env_get_location(enum env_operation op,int prio)132 enum env_location env_get_location(enum env_operation op, int prio)
133 {
134 const u32 load_magic = 0xb33fc0de;
135
136 /* Block environment access if loaded using JTAG */
137 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
138 (op != ENVOP_INIT))
139 return ENVL_UNKNOWN;
140
141 if (prio)
142 return ENVL_UNKNOWN;
143
144 return ENVL_SPI_FLASH;
145 }
146