1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <asm/global_data.h>
13 #include <linux/sizes.h>
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/mach-types.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /* ------------------------------------------------------------------------- */
27 /*
28 * Miscellaneous platform dependent initializations
29 */
30
31 #ifdef CONFIG_CMD_NAND
pm9263_nand_hw_init(void)32 static void pm9263_nand_hw_init(void)
33 {
34 unsigned long csa;
35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37
38 /* Enable CS3 */
39 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
40 writel(csa, &matrix->csa[0]);
41
42 /* Configure SMC CS3 for NAND/SmartMedia */
43 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
44 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
45 &smc->cs[3].setup);
46
47 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
48 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
49 &smc->cs[3].pulse);
50
51 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
52 &smc->cs[3].cycle);
53
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
59 AT91_SMC_MODE_DBW_8 |
60 #endif
61 AT91_SMC_MODE_TDF_CYCLE(2),
62 &smc->cs[3].mode);
63
64 /* Configure RDY/BSY */
65 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
66
67 /* Enable NandFlash */
68 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 }
70 #endif
71
72 #ifdef CONFIG_LCD
73
74 #ifdef CONFIG_LCD_IN_PSRAM
75
76 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
77 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
78
79 /* Initialize the PSRAM memory */
pm9263_lcd_hw_psram_init(void)80 static int pm9263_lcd_hw_psram_init(void)
81 {
82 unsigned long csa;
83 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
84 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
85
86 /* Enable CS3 3.3v, no pull-ups */
87 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
88 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
89
90 writel(csa, &matrix->csa[1]);
91
92 /* Configure SMC1 CS0 for PSRAM - 16-bit */
93 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
94 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
95 &smc->cs[0].setup);
96
97 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
98 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
99 &smc->cs[0].pulse);
100
101 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
102 &smc->cs[0].cycle);
103
104 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
105 &smc->cs[0].mode);
106
107 /* setup PB29 as output */
108 at91_set_pio_output(PSRAM_CRE_PIN, 1);
109
110 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
111
112 /* PSRAM: write BCR */
113 readw(PSRAM_CTRL_REG);
114 readw(PSRAM_CTRL_REG);
115 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
116 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
117
118 /* write RCR of the PSRAM */
119 readw(PSRAM_CTRL_REG);
120 readw(PSRAM_CTRL_REG);
121 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
122 /* set RCR; 0x10-async mode,0x90-page mode */
123 writew(0x90, PSRAM_CTRL_REG);
124
125 /*
126 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
127 * MT45W2M16B - CRE must be 0
128 * MT45W2M16A - CRE must be 1
129 */
130 writew(0x1234, PHYS_PSRAM);
131 writew(0x5678, PHYS_PSRAM + 2);
132
133 /* test if the chip is MT45W2M16B */
134 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
135 /* try with CRE=1 (MT45W2M16A) */
136 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
137
138 /* write RCR of the PSRAM */
139 readw(PSRAM_CTRL_REG);
140 readw(PSRAM_CTRL_REG);
141 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
142 /* set RCR;0x10-async mode,0x90-page mode */
143 writew(0x90, PSRAM_CTRL_REG);
144
145
146 writew(0x1234, PHYS_PSRAM);
147 writew(0x5678, PHYS_PSRAM+2);
148 if ((readw(PHYS_PSRAM) != 0x1234)
149 || (readw(PHYS_PSRAM + 2) != 0x5678))
150 return 1;
151
152 }
153
154 /* Bus matrix */
155 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
156 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
157
158 return 0;
159 }
160 #endif
161
pm9263_lcd_hw_init(void)162 static void pm9263_lcd_hw_init(void)
163 {
164 /* Power Control */
165 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
166 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
167
168 #ifdef CONFIG_LCD_IN_PSRAM
169 /* initialize the PSRAM */
170 int stat = pm9263_lcd_hw_psram_init();
171
172 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
173 #else
174 gd->fb_base = ATMEL_BASE_SRAM0;
175 #endif
176
177 }
178
179 #endif /* CONFIG_LCD */
180
board_early_init_f(void)181 int board_early_init_f(void)
182 {
183 return 0;
184 }
185
board_init(void)186 int board_init(void)
187 {
188 /* arch number of PM9263 Board */
189 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
190
191 /* address of boot parameters */
192 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
193
194 #ifdef CONFIG_CMD_NAND
195 pm9263_nand_hw_init();
196 #endif
197 #ifdef CONFIG_USB_OHCI_NEW
198 at91_uhp_hw_init();
199 #endif
200 #ifdef CONFIG_LCD
201 pm9263_lcd_hw_init();
202 #endif
203 return 0;
204 }
205
dram_init(void)206 int dram_init(void)
207 {
208 /* dram_init must store complete RAM size in gd->ram_size */
209 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
210 PHYS_SDRAM_SIZE);
211 return 0;
212 }
213
dram_init_banksize(void)214 int dram_init_banksize(void)
215 {
216 gd->bd->bi_dram[0].start = PHYS_SDRAM;
217 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
218
219 return 0;
220 }
221
222 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)223 int checkboard (void)
224 {
225 char *ss;
226
227 printf ("Board : Ronetix PM9263\n");
228
229 switch (gd->fb_base) {
230 case PHYS_PSRAM:
231 ss = "(PSRAM)";
232 break;
233
234 case ATMEL_BASE_SRAM0:
235 ss = "(Internal SRAM)";
236 break;
237
238 default:
239 ss = "";
240 break;
241 }
242 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
243
244 printf ("\n");
245 return 0;
246 }
247 #endif
248