1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
5 *
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
7 */
8
9 #include <init.h>
10 #include <net.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/io.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <env.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/sizes.h>
26 #include <common.h>
27 #include <fsl_esdhc_imx.h>
28 #include <mmc.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <netdev.h>
32 #include <power/pmic.h>
33 #include <power/pfuze100_pmic.h>
34 #include <usb.h>
35 #include <usb/ehci-ci.h>
36 #include <pwm.h>
37 #include <wait_bit.h>
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST)
44
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
46 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
47 PAD_CTL_SRE_FAST)
48
49 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
50
51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
52 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_SRE_FAST)
54
55 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm)
58
59 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
61
62 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
63 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
64 PAD_CTL_SRE_FAST)
65
66 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
67 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
68
69 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
70 PAD_CTL_PKE)
71
dram_init(void)72 int dram_init(void)
73 {
74 gd->ram_size = imx_ddr_size();
75
76 return 0;
77 }
78
79 static iomux_v3_cfg_t const pwm_led_pads[] = {
80 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
81 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
82 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
83 };
84
board_net_init(void)85 static int board_net_init(void)
86 {
87 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
88 unsigned char eth1addr[6];
89 int ret;
90
91 /* just to get second mac address */
92 imx_get_mac_from_fuse(1, eth1addr);
93 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
94 eth_env_set_enetaddr("eth1addr", eth1addr);
95
96 /*
97 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
98 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
99 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
100 */
101 clrsetbits_le32(&iomuxc_regs->gpr[1],
102 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
103 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
104 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
105 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
106
107 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
108 if (ret)
109 goto eth_fail;
110
111 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
112 if (ret)
113 goto eth_fail;
114
115 return ret;
116
117 eth_fail:
118 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
119 return ret;
120 }
121
122 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
123 /* I2C1 for PMIC */
124 static struct i2c_pads_info i2c_pad_info1 = {
125 .scl = {
126 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
127 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
128 .gp = IMX_GPIO_NR(1, 0),
129 },
130 .sda = {
131 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
132 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
133 .gp = IMX_GPIO_NR(1, 1),
134 },
135 };
136
pfuze_init(unsigned char i2cbus)137 static struct pmic *pfuze_init(unsigned char i2cbus)
138 {
139 struct pmic *p;
140 int ret;
141 u32 reg;
142
143 ret = power_pfuze100_init(i2cbus);
144 if (ret)
145 return NULL;
146
147 p = pmic_get("PFUZE100");
148 ret = pmic_probe(p);
149 if (ret)
150 return NULL;
151
152 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
153 printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
154
155 /* Set SW1AB stanby volage to 0.975V */
156 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
157 reg &= ~SW1x_STBY_MASK;
158 reg |= SW1x_0_975V;
159 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
160
161 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
162 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
163 reg &= ~SW1xCONF_DVSSPEED_MASK;
164 reg |= SW1xCONF_DVSSPEED_4US;
165 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
166
167 /* Set SW1C standby voltage to 0.975V */
168 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
169 reg &= ~SW1x_STBY_MASK;
170 reg |= SW1x_0_975V;
171 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
172
173 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
174 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
175 reg &= ~SW1xCONF_DVSSPEED_MASK;
176 reg |= SW1xCONF_DVSSPEED_4US;
177 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
178
179 return p;
180 }
181
pfuze_mode_init(struct pmic * p,u32 mode)182 static int pfuze_mode_init(struct pmic *p, u32 mode)
183 {
184 unsigned char offset, i, switch_num;
185 u32 id;
186 int ret;
187
188 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
189 id = id & 0xf;
190
191 if (id == 0) {
192 switch_num = 6;
193 offset = PFUZE100_SW1CMODE;
194 } else if (id == 1) {
195 switch_num = 4;
196 offset = PFUZE100_SW2MODE;
197 } else {
198 printf("Not supported, id=%d\n", id);
199 return -EINVAL;
200 }
201
202 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
203 if (ret < 0) {
204 printf("Set SW1AB mode error!\n");
205 return ret;
206 }
207
208 for (i = 0; i < switch_num - 1; i++) {
209 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
210 if (ret < 0) {
211 printf("Set switch 0x%x mode error!\n",
212 offset + i * SWITCH_SIZE);
213 return ret;
214 }
215 }
216
217 return ret;
218 }
219
power_init_board(void)220 int power_init_board(void)
221 {
222 struct pmic *p;
223 int ret;
224
225 p = pfuze_init(I2C_PMIC);
226 if (!p)
227 return -ENODEV;
228
229 ret = pfuze_mode_init(p, APS_PFM);
230 if (ret < 0)
231 return ret;
232
233 set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
234 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
235
236 return 0;
237 }
238
239 #ifdef CONFIG_USB_EHCI_MX6
240 static iomux_v3_cfg_t const usb_otg_pads[] = {
241 /* OGT1 */
242 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
243 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
244 /* OTG2 */
245 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
246 };
247
setup_iomux_usb(void)248 static void setup_iomux_usb(void)
249 {
250 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
251 ARRAY_SIZE(usb_otg_pads));
252 }
253
board_usb_phy_mode(int port)254 int board_usb_phy_mode(int port)
255 {
256 if (port == 1)
257 return USB_INIT_HOST;
258 else
259 return usb_phy_mode(port);
260 }
261 #endif
262
263 #ifdef CONFIG_PWM_IMX
set_pwm_leds(void)264 static int set_pwm_leds(void)
265 {
266 int ret;
267
268 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
269 ARRAY_SIZE(pwm_led_pads));
270 /* enable backlight PWM 2, green LED */
271 ret = pwm_init(1, 0, 0);
272 if (ret)
273 goto error;
274 /* duty cycle 200ns, period: 8000ns */
275 ret = pwm_config(1, 200, 8000);
276 if (ret)
277 goto error;
278 ret = pwm_enable(1);
279 if (ret)
280 goto error;
281
282 /* enable backlight PWM 1, blue LED */
283 ret = pwm_init(0, 0, 0);
284 if (ret)
285 goto error;
286 /* duty cycle 200ns, period: 8000ns */
287 ret = pwm_config(0, 200, 8000);
288 if (ret)
289 goto error;
290 ret = pwm_enable(0);
291 if (ret)
292 goto error;
293
294 /* enable backlight PWM 6, red LED */
295 ret = pwm_init(5, 0, 0);
296 if (ret)
297 goto error;
298 /* duty cycle 200ns, period: 8000ns */
299 ret = pwm_config(5, 200, 8000);
300 if (ret)
301 goto error;
302 ret = pwm_enable(5);
303
304 error:
305 return ret;
306 }
307 #else
set_pwm_leds(void)308 static int set_pwm_leds(void)
309 {
310 return 0;
311 }
312 #endif
313
314 #define ADCx_HC0 0x00
315 #define ADCx_HS 0x08
316 #define ADCx_HS_C0 BIT(0)
317 #define ADCx_R0 0x0c
318 #define ADCx_CFG 0x14
319 #define ADCx_CFG_SWMODE 0x308
320 #define ADCx_GC 0x18
321 #define ADCx_GC_CAL BIT(7)
322
read_adc(u32 * val)323 static int read_adc(u32 *val)
324 {
325 int ret;
326 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
327
328 /* use software mode */
329 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
330
331 /* start auto calibration */
332 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
333 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
334 if (ret)
335 goto adc_exit;
336
337 /* start conversion */
338 writel(0, b + ADCx_HC0);
339
340 /* wait for conversion */
341 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
342 if (ret)
343 goto adc_exit;
344
345 /* read result */
346 *val = readl(b + ADCx_R0);
347
348 adc_exit:
349 if (ret)
350 printf("ADC failure (ret=%i)\n", ret);
351 unmap_physmem(b, MAP_NOCACHE);
352 return ret;
353 }
354
355 #define VAL_UPPER 2498
356 #define VAL_LOWER 1550
357
set_pin_state(void)358 static int set_pin_state(void)
359 {
360 u32 val;
361 int ret;
362
363 ret = read_adc(&val);
364 if (ret)
365 return ret;
366
367 if (val >= VAL_UPPER)
368 env_set("pin_state", "connected");
369 else if (val < VAL_UPPER && val > VAL_LOWER)
370 env_set("pin_state", "open");
371 else
372 env_set("pin_state", "button");
373
374 return ret;
375 }
376
board_late_init(void)377 int board_late_init(void)
378 {
379 int ret;
380
381 ret = set_pwm_leds();
382 if (ret)
383 return ret;
384
385 ret = set_pin_state();
386
387 return ret;
388 }
389
board_early_init_f(void)390 int board_early_init_f(void)
391 {
392 setup_iomux_usb();
393
394 return 0;
395 }
396
board_init(void)397 int board_init(void)
398 {
399 /* Address of boot parameters */
400 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
401
402 #ifdef CONFIG_SYS_I2C_MXC
403 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
404 #endif
405
406 return board_net_init();
407 }
408
checkboard(void)409 int checkboard(void)
410 {
411 puts("Board: VIN|ING 2000\n");
412
413 return 0;
414 }
415
416 #define PCIE_PHY_PUP_REQ BIT(7)
417
board_preboot_os(void)418 void board_preboot_os(void)
419 {
420 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
421 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
422
423 /* Bring the PCI power domain up, so that old vendorkernel works. */
424 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
425 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
426 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
427 }
428
429 #ifdef CONFIG_SPL_BUILD
430 #include <linux/libfdt.h>
431 #include <spl.h>
432 #include <asm/arch/mx6-ddr.h>
433
434 static iomux_v3_cfg_t const pcie_pads[] = {
435 MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
436 };
437
438 static iomux_v3_cfg_t const uart_pads[] = {
439 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
440 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
441 };
442
443 static iomux_v3_cfg_t const usdhc4_pads[] = {
444 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
445 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
446 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
447 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
448 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
449 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
450 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
451 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
452 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
453 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
454 };
455
vining2000_spl_setup_iomux_pcie(void)456 static void vining2000_spl_setup_iomux_pcie(void)
457 {
458 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
459 }
460
vining2000_spl_setup_iomux_uart(void)461 static void vining2000_spl_setup_iomux_uart(void)
462 {
463 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
464 }
465
466 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
467
board_mmc_init(struct bd_info * bis)468 int board_mmc_init(struct bd_info *bis)
469 {
470 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
471
472 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
473 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
474 return fsl_esdhc_initialize(bis, &usdhc_cfg);
475 }
476
board_mmc_getcd(struct mmc * mmc)477 int board_mmc_getcd(struct mmc *mmc)
478 {
479 return 1;
480 }
481
482 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
483 .dram_dqm0 = 0x00000028,
484 .dram_dqm1 = 0x00000028,
485 .dram_dqm2 = 0x00000028,
486 .dram_dqm3 = 0x00000028,
487 .dram_ras = 0x00000028,
488 .dram_cas = 0x00000028,
489 .dram_odt0 = 0x00000028,
490 .dram_odt1 = 0x00000028,
491 .dram_sdba2 = 0x00000000,
492 .dram_sdcke0 = 0x00003000,
493 .dram_sdcke1 = 0x00003000,
494 .dram_sdclk_0 = 0x00000030,
495 .dram_sdqs0 = 0x00000028,
496 .dram_sdqs1 = 0x00000028,
497 .dram_sdqs2 = 0x00000028,
498 .dram_sdqs3 = 0x00000028,
499 .dram_reset = 0x00000028,
500 };
501
502 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
503 .grp_addds = 0x00000028,
504 .grp_b0ds = 0x00000028,
505 .grp_b1ds = 0x00000028,
506 .grp_b2ds = 0x00000028,
507 .grp_b3ds = 0x00000028,
508 .grp_ctlds = 0x00000028,
509 .grp_ddr_type = 0x000c0000,
510 .grp_ddrmode = 0x00020000,
511 .grp_ddrmode_ctl = 0x00020000,
512 .grp_ddrpke = 0x00000000,
513 };
514
515 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
516 .p0_mpwldectrl0 = 0x0022001C,
517 .p0_mpwldectrl1 = 0x001F001A,
518 .p0_mpdgctrl0 = 0x01380134,
519 .p0_mpdgctrl1 = 0x0124011C,
520 .p0_mprddlctl = 0x42404444,
521 .p0_mpwrdlctl = 0x36383C38,
522 };
523
524 static struct mx6_ddr3_cfg mem_ddr = {
525 .mem_speed = 1600,
526 .density = 4,
527 .width = 32,
528 .banks = 8,
529 .rowaddr = 15,
530 .coladdr = 10,
531 .pagesz = 2,
532 .trcd = 1391,
533 .trcmin = 4875,
534 .trasmin = 3500,
535 };
536
ccgr_init(void)537 static void ccgr_init(void)
538 {
539 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
540
541 writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
542 writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
543 writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
544 writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
545 writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
546 writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
547 writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
548 }
549
vining2000_spl_dram_init(void)550 static void vining2000_spl_dram_init(void)
551 {
552 struct mx6_ddr_sysinfo sysinfo = {
553 .dsize = mem_ddr.width / 32,
554 .cs_density = 24,
555 .ncs = 1,
556 .cs1_mirror = 0,
557 .rtt_wr = 1, /* RTT_wr = RZQ/4 */
558 .rtt_nom = 1, /* RTT_Nom = RZQ/4 */
559 .walat = 1, /* Write additional latency */
560 .ralat = 5, /* Read additional latency */
561 .mif3_mode = 3, /* Command prediction working mode */
562 .bi_on = 1, /* Bank interleaving enabled */
563 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
564 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
565 .ddr_type = DDR_TYPE_DDR3,
566 .refsel = 1, /* Refresh cycles at 32KHz */
567 .refr = 7, /* 8 refresh commands per refresh cycle */
568 };
569
570 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
571 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
572
573 /* Perform DDR DRAM calibration */
574 udelay(100);
575 mmdc_do_write_level_calibration(&sysinfo);
576 mmdc_do_dqs_calibration(&sysinfo);
577 }
578
board_init_f(ulong dummy)579 void board_init_f(ulong dummy)
580 {
581 /* setup AIPS and disable watchdog */
582 arch_cpu_init();
583
584 ccgr_init();
585
586 /* iomux setup */
587 vining2000_spl_setup_iomux_pcie();
588 vining2000_spl_setup_iomux_uart();
589
590 /* setup GP timer */
591 timer_init();
592
593 /* reset the PCIe device */
594 gpio_set_value(IMX_GPIO_NR(4, 6), 1);
595 udelay(50);
596 gpio_set_value(IMX_GPIO_NR(4, 6), 0);
597
598 /* UART clocks enabled and gd valid - init serial console */
599 preloader_console_init();
600
601 /* DDR initialization */
602 vining2000_spl_dram_init();
603
604 /* Clear the BSS. */
605 memset(__bss_start, 0, __bss_end - __bss_start);
606
607 /* load/boot image from boot device */
608 board_init_r(NULL, 0);
609 }
610 #endif
611