1.. SPDX-License-Identifier: GPL-2.0+ 2.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> 3 4Coreboot 5======== 6 7Build Instructions for U-Boot as coreboot payload 8------------------------------------------------- 9Building U-Boot as a coreboot payload is just like building U-Boot for targets 10on other architectures, like below:: 11 12 $ make coreboot_defconfig 13 $ make all 14 15Test with coreboot 16------------------ 17For testing U-Boot as the coreboot payload, there are things that need be paid 18attention to. coreboot supports loading an ELF executable and a 32-bit plain 19binary, as well as other supported payloads. With the default configuration, 20U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the 21generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool 22provided by coreboot) manually as coreboot's 'make menuconfig' does not provide 23this capability yet. The command is as follows:: 24 25 # in the coreboot root directory 26 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ 27 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000 28 29Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address 30of _x86boot_start (in arch/x86/cpu/start.S). 31 32If you want to use ELF as the coreboot payload, change U-Boot configuration to 33use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. 34 35To enable video you must enable these options in coreboot: 36 37 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) 38 - Keep VESA framebuffer 39 40At present it seems that for Minnowboard Max, coreboot does not pass through 41the video information correctly (it always says the resolution is 0x0). This 42works correctly for link though. 43 4464-bit U-Boot 45------------- 46 47In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This 48produces an image which can be booted from coreboot (32-bit). Internally it 49works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It 50can be useful for running UEFI applications, for example. 51 52This has only been lightly tested. 53 54 55Memory map 56---------- 57 58 ========== ================================================================== 59 Address Region at that address 60 ========== ================================================================== 61 ffffffff Top of ROM (and last byte of 32-bit address space) 62 7a9fd000 Typical top of memory available to U-Boot 63 (use cbsysinfo to see where memory range 'table' starts) 64 10000000 Memory reserved by coreboot for mapping PCI devices 65 (typical size 2151000, includes framebuffer) 66 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup 67 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc) 68 110000 CONFIG_BLOBLIST_ADDR (before being relocated) 69 100000 CONFIG_PRE_CON_BUF_ADDR 70 f0000 ACPI tables set up by U-Boot 71 (typically redirects to 7ab10030 or similar) 72 500 Location of coreboot sysinfo table, used during startup 73 ========== ================================================================== 74