1STMicroelectronics STM32MP1 clock tree initialization 2===================================================== 3 4The STM32MP1 clock tree initialization is based on device tree information 5for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes. 6 7RCC IP = st,stm32mp1-rcc 8======================== 9 10The RCC IP is both a reset and a clock controller but this documentation only 11describes the fields added for clock tree initialization which are not present 12in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt 13file. 14 15This parent node may optionally have additional children nodes which define 16specific init values for RCC elements. 17 18The added properties for clock tree initialization are: 19 20Required properties: 21- st,clksrc : The clock sources configuration array in a platform specific 22 order. 23 24 For the STM32MP15x family there are 9 clock sources selector which are 25 configured in the following order: 26 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 27 28 Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE> 29 from dt-bindings/clock/stm32mp1-clksrc.h. 30 31 Example: 32 st,clksrc = < 33 CLK_MPU_PLL1P 34 CLK_AXI_PLL2P 35 CLK_MCU_PLL3P 36 CLK_PLL12_HSE 37 CLK_PLL3_HSE 38 CLK_PLL4_HSE 39 CLK_RTC_LSE 40 CLK_MCO1_DISABLED 41 CLK_MCO2_DISABLED 42 >; 43 44- st,clkdiv : The clock main dividers value specified in an array 45 in a platform specific order. 46 47 When used, it shall describe the whole clock dividers tree. 48 49 For the STM32MP15x family there are 11 dividers values expected. 50 They shall be configured in the following order: 51 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2 52 53 The each divider value uses the DIV coding defined in RCC associated 54 register RCC_xxxDIVR. In most the case, it is: 55 0x0: not divided 56 0x1: division by 2 57 0x2: division by 4 58 0x3: division by 8 59 ... 60 61 Note that for RTC MCO1 MCO2, the coding is different: 62 0x0: not divided 63 0x1: division by 2 64 0x2: division by 3 65 0x3: division by 4 66 ... 67 68 Example: 69 st,clkdiv = < 70 1 /*MPU*/ 71 0 /*AXI*/ 72 0 /*MCU*/ 73 1 /*APB1*/ 74 1 /*APB2*/ 75 1 /*APB3*/ 76 1 /*APB4*/ 77 2 /*APB5*/ 78 23 /*RTC*/ 79 0 /*MCO1*/ 80 0 /*MCO2*/ 81 >; 82 83Optional Properties: 84- children for a PLL configuration with "st,stm32mp1-pll" compatible 85 86 each PLL children nodes for PLL1 to PLL4 (see ref manual for details) 87 are listed with associated reg 0 to 3. 88 PLLx is off when the associated node is absent or deactivated. 89 90 For PLL1, when the node is absent, the frequency of the OPP node is used 91 to compute the PLL setting (see compatible "operating-points-v2" in 92 opp/opp.txt for details). 93 94 Here are the available properties for each PLL node: 95 - compatible: should be "st,stm32mp1-pll" 96 97 - reg: index of the pll instance 98 99 - cfg: The parameters for PLL configuration in the following order: 100 DIVM DIVN DIVP DIVQ DIVR Output. 101 102 DIVx values are defined as in RCC spec: 103 0x0: bypass (division by 1) 104 0x1: division by 2 105 0x2: division by 3 106 0x3: division by 4 107 ... 108 109 Output contains a bitfield for each output value (1:ON/0:OFF) 110 BIT(0) => output P : DIVPEN 111 BIT(1) => output Q : DIVQEN 112 BIT(2) => output R : DIVREN 113 NB: macro PQR(p,q,r) can be used to build this value 114 with p,q,r = 0 or 1. 115 116 - frac : Fractional part of the multiplication factor 117 (optional, PLL is in integer mode when absent). 118 119 - csg : Clock Spreading Generator (optional) with parameters in the 120 following order: MOD_PER INC_STEP SSCG_MODE. 121 122 MOD_PER: Modulation Period Adjustment 123 INC_STEP: Modulation Depth Adjustment 124 SSCG_MODE: Spread spectrum clock generator mode, with associated 125 defined from stm32mp1-clksrc.h: 126 - SSCG_MODE_CENTER_SPREAD = 0 127 - SSCG_MODE_DOWN_SPREAD = 1 128 129 Example: 130 st,pll@0 { 131 compatible = "st,stm32mp1-pll"; 132 reg = <0>; 133 cfg = < 1 53 0 0 0 1 >; 134 frac = < 0x810 >; 135 }; 136 st,pll@1 { 137 compatible = "st,stm32mp1-pll"; 138 reg = <1>; 139 cfg = < 1 43 1 0 0 PQR(0,1,1) >; 140 csg = < 10 20 1 >; 141 }; 142 st,pll@2 { 143 compatible = "st,stm32mp1-pll"; 144 reg = <2>; 145 cfg = < 2 85 3 13 3 0 >; 146 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; 147 }; 148 st,pll@3 { 149 compatible = "st,stm32mp1-pll"; 150 reg = <3>; 151 cfg = < 2 78 4 7 9 3 >; 152 }; 153 154- st,pkcs : used to configure the peripherals kernel clock selection. 155 156 The property is a list of peripheral kernel clock source identifiers defined 157 by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file 158 dt-bindings/clock/stm32mp1-clksrc.h. 159 160 st,pkcs may not list all the kernel clocks and has no ordering requirements. 161 162 Example: 163 st,pkcs = < 164 CLK_STGEN_HSE 165 CLK_CKPER_HSI 166 CLK_USBPHY_PLL2P 167 CLK_DSI_PLL2Q 168 CLK_I2C46_HSI 169 CLK_UART1_HSI 170 CLK_UART24_HSI 171 >; 172 173other clocks = fixed-clock 174========================== 175 176The clock tree is also based on 5 fixed-clock in clocks node 177used to define the state of associated ST32MP1 oscillators: 178 - clk-lsi 179 - clk-lse 180 - clk-hsi 181 - clk-hse 182 - clk-csi 183 184At boot the clock tree initialization will 185 - enable oscillators present in device tree and not disabled 186 (node with status="disabled"), 187 - disable HSI oscillator if the node is absent (always activated by bootrom) 188 and not disabled (node with status="disabled"). 189 190Optional properties : 191 192a) for external oscillator: "clk-lse", "clk-hse" 193 194 4 optional fields are managed 195 - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP) 196 - "st,digbypass" configures the bypass mode as full-swing digital 197 signal (DIGBYP) 198 - "st,css" activates the clock security system (HSECSSON, LSECSSON) 199 - "st,drive" (only for LSE) contains the value of the drive for the 200 oscillator (see LSEDRV_ defined in the file 201 dt-bindings/clock/stm32mp1-clksrc.h) 202 203 Example board file: 204 / { 205 clocks { 206 clk_hse: clk-hse { 207 #clock-cells = <0>; 208 compatible = "fixed-clock"; 209 clock-frequency = <64000000>; 210 st,bypass; 211 }; 212 213 clk_lse: clk-lse { 214 #clock-cells = <0>; 215 compatible = "fixed-clock"; 216 clock-frequency = <32768>; 217 st,css; 218 st,drive = <LSEDRV_LOWEST>; 219 }; 220 }; 221 222b) for internal oscillator: "clk-hsi" 223 224 Internally HSI clock is fixed to 64MHz for STM32MP157 SoC. 225 In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC 226 doc). So this clock frequency is used to compute the expected HSI_DIV 227 for the clock tree initialization. 228 229 Example with HSIDIV = /1: 230 / { 231 clocks { 232 clk_hsi: clk-hsi { 233 #clock-cells = <0>; 234 compatible = "fixed-clock"; 235 clock-frequency = <64000000>; 236 }; 237 }; 238 239 Example with HSIDIV = /2 240 / { 241 clocks { 242 clk_hsi: clk-hsi { 243 #clock-cells = <0>; 244 compatible = "fixed-clock"; 245 clock-frequency = <32000000>; 246 }; 247 }; 248 249Example of clock tree initialization 250==================================== 251 252/ { 253 clocks { 254 u-boot,dm-pre-reloc; 255 clk_hse: clk-hse { 256 u-boot,dm-pre-reloc; 257 #clock-cells = <0>; 258 compatible = "fixed-clock"; 259 clock-frequency = <24000000>; 260 st,digbypass; 261 }; 262 263 clk_hsi: clk-hsi { 264 u-boot,dm-pre-reloc; 265 #clock-cells = <0>; 266 compatible = "fixed-clock"; 267 clock-frequency = <64000000>; 268 }; 269 270 clk_lse: clk-lse { 271 u-boot,dm-pre-reloc; 272 #clock-cells = <0>; 273 compatible = "fixed-clock"; 274 clock-frequency = <32768>; 275 }; 276 277 clk_lsi: clk-lsi { 278 u-boot,dm-pre-reloc; 279 #clock-cells = <0>; 280 compatible = "fixed-clock"; 281 clock-frequency = <32000>; 282 }; 283 284 clk_csi: clk-csi { 285 u-boot,dm-pre-reloc; 286 #clock-cells = <0>; 287 compatible = "fixed-clock"; 288 clock-frequency = <4000000>; 289 }; 290 }; 291 292 soc { 293 294 rcc: rcc@50000000 { 295 u-boot,dm-pre-reloc; 296 compatible = "st,stm32mp1-rcc", "syscon"; 297 reg = <0x50000000 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 #clock-cells = <1>; 301 #reset-cells = <1>; 302 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 303 304 st,clksrc = < 305 CLK_MPU_PLL1P 306 CLK_AXI_PLL2P 307 CLK_MCU_PLL3P 308 CLK_PLL12_HSE 309 CLK_PLL3_HSE 310 CLK_PLL4_HSE 311 CLK_RTC_LSE 312 CLK_MCO1_DISABLED 313 CLK_MCO2_DISABLED 314 >; 315 316 st,clkdiv = < 317 1 /*MPU*/ 318 0 /*AXI*/ 319 0 /*MCU*/ 320 1 /*APB1*/ 321 1 /*APB2*/ 322 1 /*APB3*/ 323 1 /*APB4*/ 324 2 /*APB5*/ 325 23 /*RTC*/ 326 0 /*MCO1*/ 327 0 /*MCO2*/ 328 >; 329 330 st,pkcs = < 331 CLK_CKPER_HSE 332 CLK_FMC_ACLK 333 CLK_QSPI_ACLK 334 CLK_ETH_DISABLED 335 CLK_SDMMC12_PLL4P 336 CLK_DSI_DSIPLL 337 CLK_STGEN_HSE 338 CLK_USBPHY_HSE 339 CLK_SPI2S1_PLL3Q 340 CLK_SPI2S23_PLL3Q 341 CLK_SPI45_HSI 342 CLK_SPI6_HSI 343 CLK_I2C46_HSI 344 CLK_SDMMC3_PLL4P 345 CLK_USBO_USBPHY 346 CLK_ADC_CKPER 347 CLK_CEC_LSE 348 CLK_I2C12_HSI 349 CLK_I2C35_HSI 350 CLK_UART1_HSI 351 CLK_UART24_HSI 352 CLK_UART35_HSI 353 CLK_UART6_HSI 354 CLK_UART78_HSI 355 CLK_SPDIF_PLL4P 356 CLK_FDCAN_PLL4Q 357 CLK_SAI1_PLL3Q 358 CLK_SAI2_PLL3Q 359 CLK_SAI3_PLL3Q 360 CLK_SAI4_PLL3Q 361 CLK_RNG1_LSI 362 CLK_RNG2_LSI 363 CLK_LPTIM1_PCLK1 364 CLK_LPTIM23_PCLK3 365 CLK_LPTIM45_LSE 366 >; 367 368 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 369 pll1: st,pll@0 { 370 compatible = "st,stm32mp1-pll"; 371 reg = <0>; 372 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 373 frac = < 0x800 >; 374 u-boot,dm-pre-reloc; 375 }; 376 377 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), 378 R = 533 (DDR) */ 379 pll2: st,pll@1 { 380 compatible = "st,stm32mp1-pll"; 381 reg = <1>; 382 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 383 frac = < 0x1400 >; 384 u-boot,dm-pre-reloc; 385 }; 386 387 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 388 pll3: st,pll@2 { 389 compatible = "st,stm32mp1-pll"; 390 reg = <2>; 391 cfg = < 1 33 1 16 36 PQR(1,1,1) >; 392 frac = < 0x1a04 >; 393 u-boot,dm-pre-reloc; 394 }; 395 396 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 397 pll4: st,pll@3 { 398 compatible = "st,stm32mp1-pll"; 399 reg = <3>; 400 cfg = < 3 98 5 7 7 PQR(1,1,1) >; 401 u-boot,dm-pre-reloc; 402 }; 403 }; 404 }; 405}; 406