1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> 4 */ 5 6 #ifndef _CLK_N5X_ 7 #define _CLK_N5X_ 8 9 #ifndef __ASSEMBLY__ 10 #include <linux/bitops.h> 11 #endif 12 13 #define CM_REG_READL(plat, reg) \ 14 readl((plat)->regs + (reg)) 15 16 #define CM_REG_WRITEL(plat, data, reg) \ 17 writel(data, (plat)->regs + (reg)) 18 19 #define CM_REG_CLRBITS(plat, reg, clear) \ 20 clrbits_le32((plat)->regs + (reg), (clear)) 21 22 #define CM_REG_SETBITS(plat, reg, set) \ 23 setbits_le32((plat)->regs + (reg), (set)) 24 25 struct cm_config { 26 /* main group */ 27 u32 main_pll_mpuclk; 28 u32 main_pll_nocclk; 29 u32 main_pll_nocdiv; 30 u32 main_pll_pllglob; 31 u32 main_pll_plldiv; 32 u32 main_pll_plloutdiv; 33 u32 spare_1[4]; 34 35 /* peripheral group */ 36 u32 per_pll_emacctl; 37 u32 per_pll_gpiodiv; 38 u32 per_pll_pllglob; 39 u32 per_pll_plldiv; 40 u32 per_pll_plloutdiv; 41 u32 spare_2[4]; 42 43 /* altera group */ 44 u32 alt_emacactr; 45 u32 alt_emacbctr; 46 u32 alt_emacptpctr; 47 u32 alt_gpiodbctr; 48 u32 alt_sdmmcctr; 49 u32 alt_s2fuser0ctr; 50 u32 alt_s2fuser1ctr; 51 u32 alt_psirefctr; 52 53 /* incoming clock */ 54 u32 hps_osc_clk_hz; 55 u32 fpga_clk_hz; 56 u32 spare_3[3]; 57 58 /* memory clock group */ 59 u32 mem_memdiv; 60 u32 mem_pllglob; 61 u32 mem_plldiv; 62 u32 mem_plloutdiv; 63 u32 spare_4[4]; 64 }; 65 66 /* Clock Manager registers */ 67 #define CLKMGR_CTRL 0 68 #define CLKMGR_STAT 4 69 #define CLKMGR_TESTIOCTRL 8 70 #define CLKMGR_INTRGEN 0x0c 71 #define CLKMGR_INTRMSK 0x10 72 #define CLKMGR_INTRCLR 0x14 73 #define CLKMGR_INTRSTS 0x18 74 #define CLKMGR_INTRSTK 0x1c 75 #define CLKMGR_INTRRAW 0x20 76 77 /* Clock Manager Main PPL group registers */ 78 #define CLKMGR_MAINPLL_EN 0x24 79 #define CLKMGR_MAINPLL_ENS 0x28 80 #define CLKMGR_MAINPLL_ENR 0x2c 81 #define CLKMGR_MAINPLL_BYPASS 0x30 82 #define CLKMGR_MAINPLL_BYPASSS 0x34 83 #define CLKMGR_MAINPLL_BYPASSR 0x38 84 #define CLKMGR_MAINPLL_MPUCLK 0x3c 85 #define CLKMGR_MAINPLL_NOCCLK 0x40 86 #define CLKMGR_MAINPLL_NOCDIV 0x44 87 #define CLKMGR_MAINPLL_PLLGLOB 0x48 88 #define CLKMGR_MAINPLL_PLLCTRL 0x4c 89 #define CLKMGR_MAINPLL_PLLDIV 0x50 90 #define CLKMGR_MAINPLL_PLLOUTDIV 0x54 91 #define CLKMGR_MAINPLL_LOSTLOCK 0x58 92 93 /* Clock Manager Peripheral PPL group registers */ 94 #define CLKMGR_PERPLL_EN 0x7c 95 #define CLKMGR_PERPLL_ENS 0x80 96 #define CLKMGR_PERPLL_ENR 0x84 97 #define CLKMGR_PERPLL_BYPASS 0x88 98 #define CLKMGR_PERPLL_BYPASSS 0x8c 99 #define CLKMGR_PERPLL_BYPASSR 0x90 100 #define CLKMGR_PERPLL_EMACCTL 0x94 101 #define CLKMGR_PERPLL_GPIODIV 0x98 102 #define CLKMGR_PERPLL_PLLGLOB 0x9c 103 #define CLKMGR_PERPLL_PLLCTRL 0xa0 104 #define CLKMGR_PERPLL_PLLDIV 0xa4 105 #define CLKMGR_PERPLL_PLLOUTDIV 0xa8 106 #define CLKMGR_PERPLL_LOSTLOCK 0xac 107 108 /* Clock Manager Altera group registers */ 109 #define CLKMGR_ALTR_EMACACTR 0xd4 110 #define CLKMGR_ALTR_EMACBCTR 0xd8 111 #define CLKMGR_ALTR_EMACPTPCTR 0xdc 112 #define CLKMGR_ALTR_GPIODBCTR 0xe0 113 #define CLKMGR_ALTR_SDMMCCTR 0xe4 114 #define CLKMGR_ALTR_S2FUSER0CTR 0xe8 115 #define CLKMGR_ALTR_S2FUSER1CTR 0xec 116 #define CLKMGR_ALTR_PSIREFCTR 0xf0 117 #define CLKMGR_ALTR_EXTCNTRST 0xf4 118 119 #define CLKMGR_CTRL_BOOTMODE BIT(0) 120 121 #define CLKMGR_STAT_BUSY BIT(0) 122 #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) 123 #define CLKMGR_STAT_MAIN_TRANS BIT(9) 124 #define CLKMGR_STAT_PERPLL_LOCKED BIT(16) 125 #define CLKMGR_STAT_PERF_TRANS BIT(17) 126 #define CLKMGR_STAT_BOOTMODE BIT(24) 127 #define CLKMGR_STAT_BOOTCLKSRC BIT(25) 128 129 #define CLKMGR_STAT_ALLPLL_LOCKED_MASK \ 130 (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED) 131 132 #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(0) 133 #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(1) 134 #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(2) 135 #define CLKMGR_INTER_PERPLLLOST_MASK BIT(3) 136 137 #define CLKMGR_CLKSRC_MASK GENMASK(18, 16) 138 #define CLKMGR_CLKSRC_OFFSET 16 139 #define CLKMGR_CLKSRC_MAIN 0 140 #define CLKMGR_CLKSRC_PER 1 141 #define CLKMGR_CLKSRC_OSC1 2 142 #define CLKMGR_CLKSRC_INTOSC 3 143 #define CLKMGR_CLKSRC_FPGA 4 144 #define CLKMGR_CLKCNT_MSK GENMASK(10, 0) 145 146 #define CLKMGR_BYPASS_MAINPLL_ALL 0x7 147 #define CLKMGR_BYPASS_PERPLL_ALL 0x7f 148 149 #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 150 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 151 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 152 #define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 153 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 154 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 155 #define CLKMGR_NOCDIV_DIVIDER_MASK 0x3 156 157 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) 158 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 159 #define CLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28) 160 #define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) 161 162 #define CLKMGR_VCO_PSRC_EOSC1 0 163 #define CLKMGR_VCO_PSRC_INTOSC 1 164 #define CLKMGR_VCO_PSRC_F2S 2 165 166 #define CLKMGR_PLLCTRL_BYPASS_MASK BIT(0) 167 #define CLKMGR_PLLCTRL_RST_N_MASK BIT(1) 168 169 #define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0) 170 #define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8) 171 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) 172 #define CLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28) 173 174 #define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0 175 #define CLKMGR_PLLDIV_FDIV_OFFSET 8 176 #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 177 #define CLKMGR_PLLDIV_RANGE_OFFSET 28 178 179 #define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) 180 #define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8) 181 #define CLKMGR_PLLOUTDIV_C2CNT_MASK GENMASK(20, 16) 182 #define CLKMGR_PLLOUTDIV_C3CNT_MASK GENMASK(28, 24) 183 184 #define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 185 #define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8 186 #define CLKMGR_PLLOUTDIV_C2CNT_OFFSET 16 187 #define CLKMGR_PLLOUTDIV_C3CNT_OFFSET 24 188 189 #define CLKMGR_PLLCX_EN_SET_MSK BIT(27) 190 #define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28) 191 192 #define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) 193 #define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 194 #define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) 195 #define CLKMGR_VCOCALIB_MSCNT_CONST 100 196 #define CLKMGR_VCOCALIB_HSCNT_CONST 4 197 198 #define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) 199 200 #define CLKMGR_LOSTLOCK_SET_MASK BIT(0) 201 202 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) 203 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 204 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) 205 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 206 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) 207 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 208 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28) 209 210 #define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16 211 #define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16) 212 #define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0 213 #define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0) 214 215 #define CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK GENMASK(15, 0) 216 217 #endif /* _CLK_N5X_ */ 218