1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <dm/device-internal.h>
10 #include <linux/clk-provider.h>
11
12 #define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
13 #define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
14
clk_fixed_rate_get_rate(struct clk * clk)15 static ulong clk_fixed_rate_get_rate(struct clk *clk)
16 {
17 return to_clk_fixed_rate(clk->dev)->fixed_rate;
18 }
19
20 /* avoid clk_enable() return -ENOSYS */
dummy_enable(struct clk * clk)21 static int dummy_enable(struct clk *clk)
22 {
23 return 0;
24 }
25
26 const struct clk_ops clk_fixed_rate_ops = {
27 .get_rate = clk_fixed_rate_get_rate,
28 .enable = dummy_enable,
29 .disable = dummy_enable,
30 };
31
clk_fixed_rate_ofdata_to_plat_(struct udevice * dev,struct clk_fixed_rate * plat)32 void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
33 struct clk_fixed_rate *plat)
34 {
35 struct clk *clk = &plat->clk;
36 if (CONFIG_IS_ENABLED(OF_REAL))
37 plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency",
38 0);
39
40 /* Make fixed rate clock accessible from higher level struct clk */
41 /* FIXME: This is not allowed */
42 dev_set_uclass_priv(dev, clk);
43
44 clk->dev = dev;
45 clk->enable_count = 0;
46 }
47
clk_fixed_rate_raw_get_rate(struct clk * clk)48 static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
49 {
50 return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
51 }
52
53 const struct clk_ops clk_fixed_rate_raw_ops = {
54 .get_rate = clk_fixed_rate_raw_get_rate,
55 };
56
clk_fixed_rate_of_to_plat(struct udevice * dev)57 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
58 {
59 clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
60
61 return 0;
62 }
63
64 #if CONFIG_IS_ENABLED(CLK_CCF)
clk_register_fixed_rate(struct device * dev,const char * name,ulong rate)65 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
66 ulong rate)
67 {
68 struct clk *clk;
69 struct clk_fixed_rate *fixed;
70 int ret;
71
72 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
73 if (!fixed)
74 return ERR_PTR(-ENOMEM);
75
76 fixed->fixed_rate = rate;
77
78 clk = &fixed->clk;
79
80 ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
81 if (ret) {
82 kfree(fixed);
83 return ERR_PTR(ret);
84 }
85
86 return clk;
87 }
88 #endif
89
90 static const struct udevice_id clk_fixed_rate_match[] = {
91 {
92 .compatible = "fixed-clock",
93 },
94 { /* sentinel */ }
95 };
96
97 U_BOOT_DRIVER(fixed_clock) = {
98 .name = "fixed_clock",
99 .id = UCLASS_CLK,
100 .of_match = clk_fixed_rate_match,
101 .of_to_plat = clk_fixed_rate_of_to_plat,
102 .plat_auto = sizeof(struct clk_fixed_rate),
103 .ops = &clk_fixed_rate_ops,
104 .flags = DM_FLAG_PRE_RELOC,
105 };
106
107 U_BOOT_DRIVER(clk_fixed_rate_raw) = {
108 .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
109 .id = UCLASS_CLK,
110 .ops = &clk_fixed_rate_raw_ops,
111 .flags = DM_FLAG_PRE_RELOC,
112 };
113