1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * Copyright (C) 2018 Renesas Electronics Corp. 7 * 8 */ 9 10 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 13 enum rcar_gen3_clk_types { 14 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 15 CLK_TYPE_GEN3_PLL0, 16 CLK_TYPE_GEN3_PLL1, 17 CLK_TYPE_GEN3_PLL2, 18 CLK_TYPE_GEN3_PLL3, 19 CLK_TYPE_GEN3_PLL4, 20 CLK_TYPE_GEN3_SD, 21 CLK_TYPE_GEN3_R, 22 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 23 CLK_TYPE_GEN3_Z, 24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 26 CLK_TYPE_GEN3_RPCSRC, 27 CLK_TYPE_GEN3_E3_RPCSRC, 28 CLK_TYPE_GEN3_RPC, 29 CLK_TYPE_GEN3_RPCD2, 30 31 CLK_TYPE_R8A779A0_MAIN, 32 CLK_TYPE_R8A779A0_PLL1, 33 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 34 CLK_TYPE_R8A779A0_PLL5, 35 CLK_TYPE_R8A779A0_SD, 36 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 37 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 38 39 /* SoC specific definitions start here */ 40 CLK_TYPE_GEN3_SOC_BASE, 41 }; 42 43 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 45 46 #define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \ 47 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset) 48 49 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 50 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 51 (_parent0) << 16 | (_parent1), \ 52 .div = (_div0) << 16 | (_div1), .offset = _md) 53 54 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 55 _div_clean) \ 56 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 57 _parent_clean, _div_clean) 58 59 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 60 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 61 62 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 63 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 64 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 65 66 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ 67 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 68 69 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ 70 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ 71 (_parent0) << 16 | (_parent1), .div = 8) 72 73 struct rcar_gen3_cpg_pll_config { 74 u8 extal_div; 75 u8 pll1_mult; 76 u8 pll1_div; 77 u8 pll3_mult; 78 u8 pll3_div; 79 u8 osc_prediv; 80 u8 pll5_mult; 81 u8 pll5_div; 82 }; 83 84 #define CPG_RST_MODEMR 0x060 85 86 #define CPG_RPCCKCR 0x238 87 #define CPG_RCKCR 0x240 88 89 struct gen3_clk_priv { 90 void __iomem *base; 91 struct cpg_mssr_info *info; 92 struct clk clk_extal; 93 struct clk clk_extalr; 94 bool sscg; 95 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 96 }; 97 98 int gen3_clk_probe(struct udevice *dev); 99 int gen3_clk_remove(struct udevice *dev); 100 101 extern const struct clk_ops gen3_clk_ops; 102 103 #endif 104