1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <syscon.h>
13 #include <asm/io.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk322x.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <dm/device-internal.h>
18 #include <dm/lists.h>
19 #include <dt-bindings/clock/rk3228-cru.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/log2.h>
23 #include <linux/stringify.h>
24
25 enum {
26 VCO_MAX_HZ = 3200U * 1000000,
27 VCO_MIN_HZ = 800 * 1000000,
28 OUTPUT_MAX_HZ = 3200U * 1000000,
29 OUTPUT_MIN_HZ = 24 * 1000000,
30 };
31
32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
33
34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
35 .refdiv = _refdiv,\
36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
37 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
38 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
39 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
40 #hz "Hz cannot be hit with PLL "\
41 "divisors on line " __stringify(__LINE__));
42
43 /* use integer mode*/
44 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
45 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
46
rkclk_set_pll(struct rk322x_cru * cru,enum rk_clk_id clk_id,const struct pll_div * div)47 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
48 const struct pll_div *div)
49 {
50 int pll_id = rk_pll_id(clk_id);
51 struct rk322x_pll *pll = &cru->pll[pll_id];
52
53 /* All PLLs have same VCO and output frequency range restrictions. */
54 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
55 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
56
57 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
58 pll, div->fbdiv, div->refdiv, div->postdiv1,
59 div->postdiv2, vco_hz, output_hz);
60 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
61 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
62
63 /* use integer mode */
64 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
65 /* Power down */
66 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
67
68 rk_clrsetreg(&pll->con0,
69 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
70 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
71 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
72 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
73 div->refdiv << PLL_REFDIV_SHIFT));
74
75 /* Power Up */
76 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
77
78 /* waiting for pll lock */
79 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
80 udelay(1);
81
82 return 0;
83 }
84
rkclk_init(struct rk322x_cru * cru)85 static void rkclk_init(struct rk322x_cru *cru)
86 {
87 u32 aclk_div;
88 u32 hclk_div;
89 u32 pclk_div;
90
91 /* pll enter slow-mode */
92 rk_clrsetreg(&cru->cru_mode_con,
93 GPLL_MODE_MASK | APLL_MODE_MASK,
94 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
95 APLL_MODE_SLOW << APLL_MODE_SHIFT);
96
97 /* init pll */
98 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
99 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
100
101 /*
102 * select apll as cpu/core clock pll source and
103 * set up dependent divisors for PERI and ACLK clocks.
104 * core hz : apll = 1:1
105 */
106 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
107 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
108
109 pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
110 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
111
112 rk_clrsetreg(&cru->cru_clksel_con[0],
113 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
114 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
115 0 << CORE_DIV_CON_SHIFT);
116
117 rk_clrsetreg(&cru->cru_clksel_con[1],
118 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
119 aclk_div << CORE_ACLK_DIV_SHIFT |
120 pclk_div << CORE_PERI_DIV_SHIFT);
121
122 /*
123 * select gpll as pd_bus bus clock source and
124 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
125 */
126 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
127 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
128
129 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
130 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
131
132 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
133 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
134
135 rk_clrsetreg(&cru->cru_clksel_con[0],
136 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
137 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
138 aclk_div << BUS_ACLK_DIV_SHIFT);
139
140 rk_clrsetreg(&cru->cru_clksel_con[1],
141 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
142 pclk_div << BUS_PCLK_DIV_SHIFT |
143 hclk_div << BUS_HCLK_DIV_SHIFT);
144
145 /*
146 * select gpll as pd_peri bus clock source and
147 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
148 */
149 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
150 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
151
152 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
153 assert((1 << hclk_div) * PERI_HCLK_HZ ==
154 PERI_ACLK_HZ && (hclk_div < 0x4));
155
156 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
157 assert((1 << pclk_div) * PERI_PCLK_HZ ==
158 PERI_ACLK_HZ && pclk_div < 0x8);
159
160 rk_clrsetreg(&cru->cru_clksel_con[10],
161 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
162 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
163 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
164 pclk_div << PERI_PCLK_DIV_SHIFT |
165 hclk_div << PERI_HCLK_DIV_SHIFT |
166 aclk_div << PERI_ACLK_DIV_SHIFT);
167
168 /* PLL enter normal-mode */
169 rk_clrsetreg(&cru->cru_mode_con,
170 GPLL_MODE_MASK | APLL_MODE_MASK,
171 GPLL_MODE_NORM << GPLL_MODE_SHIFT |
172 APLL_MODE_NORM << APLL_MODE_SHIFT);
173 }
174
175 /* Get pll rate by id */
rkclk_pll_get_rate(struct rk322x_cru * cru,enum rk_clk_id clk_id)176 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
177 enum rk_clk_id clk_id)
178 {
179 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
180 uint32_t con;
181 int pll_id = rk_pll_id(clk_id);
182 struct rk322x_pll *pll = &cru->pll[pll_id];
183 static u8 clk_shift[CLK_COUNT] = {
184 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
185 GPLL_MODE_SHIFT, 0xff
186 };
187 static u32 clk_mask[CLK_COUNT] = {
188 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
189 GPLL_MODE_MASK, 0xff
190 };
191 uint shift;
192 uint mask;
193
194 con = readl(&cru->cru_mode_con);
195 shift = clk_shift[clk_id];
196 mask = clk_mask[clk_id];
197
198 switch ((con & mask) >> shift) {
199 case GPLL_MODE_SLOW:
200 return OSC_HZ;
201 case GPLL_MODE_NORM:
202
203 /* normal mode */
204 con = readl(&pll->con0);
205 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
206 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
207 con = readl(&pll->con1);
208 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
209 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
210 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
211 default:
212 return 32768;
213 }
214 }
215
rockchip_mmc_get_clk(struct rk322x_cru * cru,uint clk_general_rate,int periph)216 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
217 int periph)
218 {
219 uint src_rate;
220 uint div, mux;
221 u32 con;
222
223 switch (periph) {
224 case HCLK_EMMC:
225 case SCLK_EMMC:
226 case SCLK_EMMC_SAMPLE:
227 con = readl(&cru->cru_clksel_con[11]);
228 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
229 con = readl(&cru->cru_clksel_con[12]);
230 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
231 break;
232 case HCLK_SDMMC:
233 case SCLK_SDMMC:
234 con = readl(&cru->cru_clksel_con[11]);
235 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
236 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
243 return DIV_TO_RATE(src_rate, div) / 2;
244 }
245
rk322x_mac_set_clk(struct rk322x_cru * cru,uint freq)246 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
247 {
248 ulong ret;
249
250 /*
251 * The gmac clock can be derived either from an external clock
252 * or can be generated from internally by a divider from SCLK_MAC.
253 */
254 if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
255 /* An external clock will always generate the right rate... */
256 ret = freq;
257 } else {
258 u32 con = readl(&cru->cru_clksel_con[5]);
259 ulong pll_rate;
260 u8 div;
261
262 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
263 pll_rate = GPLL_HZ;
264 else
265 /* CPLL is not set */
266 return -EPERM;
267
268 div = DIV_ROUND_UP(pll_rate, freq) - 1;
269 if (div <= 0x1f)
270 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
271 div << CLK_MAC_DIV_SHIFT);
272 else
273 debug("Unsupported div for gmac:%d\n", div);
274
275 return DIV_TO_RATE(pll_rate, div);
276 }
277
278 return ret;
279 }
280
rockchip_mmc_set_clk(struct rk322x_cru * cru,uint clk_general_rate,int periph,uint freq)281 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
282 int periph, uint freq)
283 {
284 int src_clk_div;
285 int mux;
286
287 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
288
289 /* mmc clock defaulg div 2 internal, need provide double in cru */
290 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
291
292 if (src_clk_div > 128) {
293 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
294 assert(src_clk_div - 1 < 128);
295 mux = EMMC_SEL_24M;
296 } else {
297 mux = EMMC_SEL_GPLL;
298 }
299
300 switch (periph) {
301 case HCLK_EMMC:
302 case SCLK_EMMC:
303 case SCLK_EMMC_SAMPLE:
304 rk_clrsetreg(&cru->cru_clksel_con[11],
305 EMMC_PLL_MASK,
306 mux << EMMC_PLL_SHIFT);
307 rk_clrsetreg(&cru->cru_clksel_con[12],
308 EMMC_DIV_MASK,
309 (src_clk_div - 1) << EMMC_DIV_SHIFT);
310 break;
311 case HCLK_SDMMC:
312 case SCLK_SDMMC:
313 rk_clrsetreg(&cru->cru_clksel_con[11],
314 MMC0_PLL_MASK | MMC0_DIV_MASK,
315 mux << MMC0_PLL_SHIFT |
316 (src_clk_div - 1) << MMC0_DIV_SHIFT);
317 break;
318 default:
319 return -EINVAL;
320 }
321
322 return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
323 }
324
rk322x_ddr_set_clk(struct rk322x_cru * cru,unsigned int set_rate)325 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
326 {
327 struct pll_div dpll_cfg;
328
329 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
330 switch (set_rate) {
331 case 400*MHz:
332 dpll_cfg = (struct pll_div)
333 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
334 break;
335 case 600*MHz:
336 dpll_cfg = (struct pll_div)
337 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
338 break;
339 case 800*MHz:
340 dpll_cfg = (struct pll_div)
341 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
342 break;
343 }
344
345 /* pll enter slow-mode */
346 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
347 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
348 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
349 /* PLL enter normal-mode */
350 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
351 DPLL_MODE_NORM << DPLL_MODE_SHIFT);
352
353 return set_rate;
354 }
rk322x_clk_get_rate(struct clk * clk)355 static ulong rk322x_clk_get_rate(struct clk *clk)
356 {
357 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
358 ulong rate, gclk_rate;
359
360 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
361 switch (clk->id) {
362 case 0 ... 63:
363 rate = rkclk_pll_get_rate(priv->cru, clk->id);
364 break;
365 case HCLK_EMMC:
366 case SCLK_EMMC:
367 case HCLK_SDMMC:
368 case SCLK_SDMMC:
369 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
370 break;
371 default:
372 return -ENOENT;
373 }
374
375 return rate;
376 }
377
rk322x_clk_set_rate(struct clk * clk,ulong rate)378 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
379 {
380 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
381 ulong new_rate, gclk_rate;
382
383 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
384 switch (clk->id) {
385 case HCLK_EMMC:
386 case SCLK_EMMC:
387 case HCLK_SDMMC:
388 case SCLK_SDMMC:
389 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
390 clk->id, rate);
391 break;
392 case CLK_DDR:
393 new_rate = rk322x_ddr_set_clk(priv->cru, rate);
394 break;
395 case SCLK_MAC:
396 new_rate = rk322x_mac_set_clk(priv->cru, rate);
397 break;
398 case PLL_GPLL:
399 return 0;
400 default:
401 return -ENOENT;
402 }
403
404 return new_rate;
405 }
406
rk322x_gmac_set_parent(struct clk * clk,struct clk * parent)407 static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
408 {
409 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
410 struct rk322x_cru *cru = priv->cru;
411
412 /*
413 * If the requested parent is in the same clock-controller and the id
414 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
415 */
416 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
417 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
418 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
419 return 0;
420 }
421
422 /*
423 * If the requested parent is in the same clock-controller and the id
424 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
425 */
426 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
427 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
428 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
429 return 0;
430 }
431
432 return -EINVAL;
433 }
434
rk322x_gmac_extclk_set_parent(struct clk * clk,struct clk * parent)435 static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
436 {
437 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
438 const char *clock_output_name;
439 struct rk322x_cru *cru = priv->cru;
440 int ret;
441
442 ret = dev_read_string_index(parent->dev, "clock-output-names",
443 parent->id, &clock_output_name);
444 if (ret < 0)
445 return -ENODATA;
446
447 if (!strcmp(clock_output_name, "ext_gmac")) {
448 debug("%s: switching gmac extclk to ext_gmac\n", __func__);
449 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
450 return 0;
451 } else if (!strcmp(clock_output_name, "phy_50m_out")) {
452 debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
453 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
454 return 0;
455 }
456
457 return -EINVAL;
458 }
459
rk322x_clk_set_parent(struct clk * clk,struct clk * parent)460 static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
461 {
462 switch (clk->id) {
463 case SCLK_MAC:
464 return rk322x_gmac_set_parent(clk, parent);
465 case SCLK_MAC_EXTCLK:
466 return rk322x_gmac_extclk_set_parent(clk, parent);
467 }
468
469 debug("%s: unsupported clk %ld\n", __func__, clk->id);
470 return -ENOENT;
471 }
472
473 static struct clk_ops rk322x_clk_ops = {
474 .get_rate = rk322x_clk_get_rate,
475 .set_rate = rk322x_clk_set_rate,
476 .set_parent = rk322x_clk_set_parent,
477 };
478
rk322x_clk_of_to_plat(struct udevice * dev)479 static int rk322x_clk_of_to_plat(struct udevice *dev)
480 {
481 struct rk322x_clk_priv *priv = dev_get_priv(dev);
482
483 priv->cru = dev_read_addr_ptr(dev);
484
485 return 0;
486 }
487
rk322x_clk_probe(struct udevice * dev)488 static int rk322x_clk_probe(struct udevice *dev)
489 {
490 struct rk322x_clk_priv *priv = dev_get_priv(dev);
491
492 rkclk_init(priv->cru);
493
494 return 0;
495 }
496
rk322x_clk_bind(struct udevice * dev)497 static int rk322x_clk_bind(struct udevice *dev)
498 {
499 int ret;
500 struct udevice *sys_child;
501 struct sysreset_reg *priv;
502
503 /* The reset driver does not have a device node, so bind it here */
504 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
505 &sys_child);
506 if (ret) {
507 debug("Warning: No sysreset driver: ret=%d\n", ret);
508 } else {
509 priv = malloc(sizeof(struct sysreset_reg));
510 priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
511 cru_glb_srst_fst_value);
512 priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
513 cru_glb_srst_snd_value);
514 dev_set_priv(sys_child, priv);
515 }
516
517 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
518 ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
519 ret = rockchip_reset_bind(dev, ret, 9);
520 if (ret)
521 debug("Warning: software reset driver bind faile\n");
522 #endif
523
524 return 0;
525 }
526
527 static const struct udevice_id rk322x_clk_ids[] = {
528 { .compatible = "rockchip,rk3228-cru" },
529 { }
530 };
531
532 U_BOOT_DRIVER(rockchip_rk322x_cru) = {
533 .name = "clk_rk322x",
534 .id = UCLASS_CLK,
535 .of_match = rk322x_clk_ids,
536 .priv_auto = sizeof(struct rk322x_clk_priv),
537 .of_to_plat = rk322x_clk_of_to_plat,
538 .ops = &rk322x_clk_ops,
539 .bind = rk322x_clk_bind,
540 .probe = rk322x_clk_probe,
541 };
542