1menu "i.MX8ULP DDR controllers"
2 depends on ARCH_IMX8ULP
3
4config IMX8ULP_DRAM
5 bool "imx8m dram"
6
7config IMX8ULP_DRAM_PHY_PLL_BYPASS
8 bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
9 depends on IMX8ULP_DRAM
10
11endmenu
12