1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
4 */
5
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <malloc.h>
10 #include <asm/global_data.h>
11 #include <dm/device_compat.h>
12 #include <dm/pinctrl.h>
13 #include <errno.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include "../pinctrl/renesas/sh_pfc.h"
18
19 #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
20 #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
21 #define GPIO_OUTDT 0x08 /* General Output Register */
22 #define GPIO_INDT 0x0c /* General Input Register */
23 #define GPIO_INTDT 0x10 /* Interrupt Display Register */
24 #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
25 #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
26 #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
27 #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
28 #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
29 #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
30 #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
31 #define GPIO_INEN 0x50 /* General Input Enable Register */
32
33 #define RCAR_MAX_GPIO_PER_BANK 32
34
35 #define RCAR_GPIO_HAS_INEN BIT(0)
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 struct rcar_gpio_priv {
40 void __iomem *regs;
41 u32 quirks;
42 int pfc_offset;
43 };
44
rcar_gpio_get_value(struct udevice * dev,unsigned offset)45 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
46 {
47 struct rcar_gpio_priv *priv = dev_get_priv(dev);
48 const u32 bit = BIT(offset);
49
50 /*
51 * Testing on r8a7790 shows that INDT does not show correct pin state
52 * when configured as output, so use OUTDT in case of output pins.
53 */
54 if (readl(priv->regs + GPIO_INOUTSEL) & bit)
55 return !!(readl(priv->regs + GPIO_OUTDT) & bit);
56 else
57 return !!(readl(priv->regs + GPIO_INDT) & bit);
58 }
59
rcar_gpio_set_value(struct udevice * dev,unsigned offset,int value)60 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
61 int value)
62 {
63 struct rcar_gpio_priv *priv = dev_get_priv(dev);
64
65 if (value)
66 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
67 else
68 clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
69
70 return 0;
71 }
72
rcar_gpio_set_direction(struct udevice * dev,unsigned offset,bool output)73 static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
74 bool output)
75 {
76 struct rcar_gpio_priv *priv = dev_get_priv(dev);
77 void __iomem *regs = priv->regs;
78
79 /*
80 * follow steps in the GPIO documentation for
81 * "Setting General Output Mode" and
82 * "Setting General Input Mode"
83 */
84
85 /* Configure postive logic in POSNEG */
86 clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
87
88 /* Select "Input Enable/Disable" in INEN */
89 if (priv->quirks & RCAR_GPIO_HAS_INEN) {
90 if (output)
91 clrbits_le32(regs + GPIO_INEN, BIT(offset));
92 else
93 setbits_le32(regs + GPIO_INEN, BIT(offset));
94 }
95
96 /* Select "General Input/Output Mode" in IOINTSEL */
97 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
98
99 /* Select Input Mode or Output Mode in INOUTSEL */
100 if (output)
101 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
102 else
103 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
104 }
105
rcar_gpio_direction_input(struct udevice * dev,unsigned offset)106 static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
107 {
108 rcar_gpio_set_direction(dev, offset, false);
109
110 return 0;
111 }
112
rcar_gpio_direction_output(struct udevice * dev,unsigned offset,int value)113 static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
114 int value)
115 {
116 /* write GPIO value to output before selecting output mode of pin */
117 rcar_gpio_set_value(dev, offset, value);
118 rcar_gpio_set_direction(dev, offset, true);
119
120 return 0;
121 }
122
rcar_gpio_get_function(struct udevice * dev,unsigned offset)123 static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
124 {
125 struct rcar_gpio_priv *priv = dev_get_priv(dev);
126
127 if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
128 return GPIOF_OUTPUT;
129 else
130 return GPIOF_INPUT;
131 }
132
rcar_gpio_request(struct udevice * dev,unsigned offset,const char * label)133 static int rcar_gpio_request(struct udevice *dev, unsigned offset,
134 const char *label)
135 {
136 return pinctrl_gpio_request(dev, offset);
137 }
138
rcar_gpio_free(struct udevice * dev,unsigned offset)139 static int rcar_gpio_free(struct udevice *dev, unsigned offset)
140 {
141 return pinctrl_gpio_free(dev, offset);
142 }
143
144 static const struct dm_gpio_ops rcar_gpio_ops = {
145 .request = rcar_gpio_request,
146 .rfree = rcar_gpio_free,
147 .direction_input = rcar_gpio_direction_input,
148 .direction_output = rcar_gpio_direction_output,
149 .get_value = rcar_gpio_get_value,
150 .set_value = rcar_gpio_set_value,
151 .get_function = rcar_gpio_get_function,
152 };
153
rcar_gpio_probe(struct udevice * dev)154 static int rcar_gpio_probe(struct udevice *dev)
155 {
156 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
157 struct rcar_gpio_priv *priv = dev_get_priv(dev);
158 struct fdtdec_phandle_args args;
159 struct clk clk;
160 int node = dev_of_offset(dev);
161 int ret;
162
163 priv->regs = dev_read_addr_ptr(dev);
164 priv->quirks = dev_get_driver_data(dev);
165 uc_priv->bank_name = dev->name;
166
167 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
168 NULL, 3, 0, &args);
169 priv->pfc_offset = ret == 0 ? args.args[1] : -1;
170 uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
171
172 ret = clk_get_by_index(dev, 0, &clk);
173 if (ret < 0) {
174 dev_err(dev, "Failed to get GPIO bank clock\n");
175 return ret;
176 }
177
178 ret = clk_enable(&clk);
179 clk_free(&clk);
180 if (ret) {
181 dev_err(dev, "Failed to enable GPIO bank clock\n");
182 return ret;
183 }
184
185 return 0;
186 }
187
188 static const struct udevice_id rcar_gpio_ids[] = {
189 { .compatible = "renesas,gpio-r8a7795" },
190 { .compatible = "renesas,gpio-r8a7796" },
191 { .compatible = "renesas,gpio-r8a77965" },
192 { .compatible = "renesas,gpio-r8a77970" },
193 { .compatible = "renesas,gpio-r8a77990" },
194 { .compatible = "renesas,gpio-r8a77995" },
195 { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
196 { .compatible = "renesas,rcar-gen2-gpio" },
197 { .compatible = "renesas,rcar-gen3-gpio" },
198 { /* sentinel */ }
199 };
200
201 U_BOOT_DRIVER(rcar_gpio) = {
202 .name = "rcar-gpio",
203 .id = UCLASS_GPIO,
204 .of_match = rcar_gpio_ids,
205 .ops = &rcar_gpio_ops,
206 .priv_auto = sizeof(struct rcar_gpio_priv),
207 .probe = rcar_gpio_probe,
208 };
209