1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 *
5 * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
6 *
7 * (C) Copyright 2007-2011
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 * Tom Cubie <tangliang@allwinnertech.com>
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <fdtdec.h>
16 #include <malloc.h>
17 #include <asm/io.h>
18 #include <asm/gpio.h>
19 #include <dm/device-internal.h>
20 #include <dt-bindings/gpio/gpio.h>
21
22 struct sunxi_gpio_plat {
23 struct sunxi_gpio *regs;
24 const char *bank_name; /* Name of bank, e.g. "B" */
25 int gpio_count;
26 };
27
28 #if !CONFIG_IS_ENABLED(DM_GPIO)
sunxi_gpio_output(u32 pin,u32 val)29 static int sunxi_gpio_output(u32 pin, u32 val)
30 {
31 u32 dat;
32 u32 bank = GPIO_BANK(pin);
33 u32 num = GPIO_NUM(pin);
34 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
35
36 dat = readl(&pio->dat);
37 if (val)
38 dat |= 0x1 << num;
39 else
40 dat &= ~(0x1 << num);
41
42 writel(dat, &pio->dat);
43
44 return 0;
45 }
46
sunxi_gpio_input(u32 pin)47 static int sunxi_gpio_input(u32 pin)
48 {
49 u32 dat;
50 u32 bank = GPIO_BANK(pin);
51 u32 num = GPIO_NUM(pin);
52 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
53
54 dat = readl(&pio->dat);
55 dat >>= num;
56
57 return dat & 0x1;
58 }
59
gpio_request(unsigned gpio,const char * label)60 int gpio_request(unsigned gpio, const char *label)
61 {
62 return 0;
63 }
64
gpio_free(unsigned gpio)65 int gpio_free(unsigned gpio)
66 {
67 return 0;
68 }
69
gpio_direction_input(unsigned gpio)70 int gpio_direction_input(unsigned gpio)
71 {
72 sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
73
74 return 0;
75 }
76
gpio_direction_output(unsigned gpio,int value)77 int gpio_direction_output(unsigned gpio, int value)
78 {
79 sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
80
81 return sunxi_gpio_output(gpio, value);
82 }
83
gpio_get_value(unsigned gpio)84 int gpio_get_value(unsigned gpio)
85 {
86 return sunxi_gpio_input(gpio);
87 }
88
gpio_set_value(unsigned gpio,int value)89 int gpio_set_value(unsigned gpio, int value)
90 {
91 return sunxi_gpio_output(gpio, value);
92 }
93
sunxi_name_to_gpio(const char * name)94 int sunxi_name_to_gpio(const char *name)
95 {
96 int group = 0;
97 int groupsize = 9 * 32;
98 long pin;
99 char *eptr;
100
101 if (*name == 'P' || *name == 'p')
102 name++;
103 if (*name >= 'A') {
104 group = *name - (*name > 'a' ? 'a' : 'A');
105 groupsize = 32;
106 name++;
107 }
108
109 pin = simple_strtol(name, &eptr, 10);
110 if (!*name || *eptr)
111 return -1;
112 if (pin < 0 || pin > groupsize || group >= 9)
113 return -1;
114 return group * 32 + pin;
115 }
116 #endif /* DM_GPIO */
117
118 #if CONFIG_IS_ENABLED(DM_GPIO)
119 /* TODO(sjg@chromium.org): Remove this function and use device tree */
sunxi_name_to_gpio(const char * name)120 int sunxi_name_to_gpio(const char *name)
121 {
122 unsigned int gpio;
123 int ret;
124 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
125 char lookup[8];
126
127 if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
128 sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
129 SUNXI_GPIO_AXP0_VBUS_DETECT);
130 name = lookup;
131 } else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
132 sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
133 SUNXI_GPIO_AXP0_VBUS_ENABLE);
134 name = lookup;
135 }
136 #endif
137 ret = gpio_lookup_name(name, NULL, NULL, &gpio);
138
139 return ret ? ret : gpio;
140 }
141
sunxi_gpio_direction_input(struct udevice * dev,unsigned offset)142 static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
143 {
144 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
145
146 sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
147
148 return 0;
149 }
150
sunxi_gpio_direction_output(struct udevice * dev,unsigned offset,int value)151 static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
152 int value)
153 {
154 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
155 u32 num = GPIO_NUM(offset);
156
157 sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
158 clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
159
160 return 0;
161 }
162
sunxi_gpio_get_value(struct udevice * dev,unsigned offset)163 static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
164 {
165 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
166 u32 num = GPIO_NUM(offset);
167 unsigned dat;
168
169 dat = readl(&plat->regs->dat);
170 dat >>= num;
171
172 return dat & 0x1;
173 }
174
sunxi_gpio_set_value(struct udevice * dev,unsigned offset,int value)175 static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
176 int value)
177 {
178 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
179 u32 num = GPIO_NUM(offset);
180
181 clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
182 return 0;
183 }
184
sunxi_gpio_get_function(struct udevice * dev,unsigned offset)185 static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
186 {
187 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
188 int func;
189
190 func = sunxi_gpio_get_cfgbank(plat->regs, offset);
191 if (func == SUNXI_GPIO_OUTPUT)
192 return GPIOF_OUTPUT;
193 else if (func == SUNXI_GPIO_INPUT)
194 return GPIOF_INPUT;
195 else
196 return GPIOF_FUNC;
197 }
198
sunxi_gpio_xlate(struct udevice * dev,struct gpio_desc * desc,struct ofnode_phandle_args * args)199 static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
200 struct ofnode_phandle_args *args)
201 {
202 int ret;
203
204 ret = device_get_child(dev, args->args[0], &desc->dev);
205 if (ret)
206 return ret;
207 desc->offset = args->args[1];
208 desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
209
210 return 0;
211 }
212
213 static const struct dm_gpio_ops gpio_sunxi_ops = {
214 .direction_input = sunxi_gpio_direction_input,
215 .direction_output = sunxi_gpio_direction_output,
216 .get_value = sunxi_gpio_get_value,
217 .set_value = sunxi_gpio_set_value,
218 .get_function = sunxi_gpio_get_function,
219 .xlate = sunxi_gpio_xlate,
220 };
221
222 /**
223 * Returns the name of a GPIO bank
224 *
225 * GPIO banks are named A, B, C, ...
226 *
227 * @bank: Bank number (0, 1..n-1)
228 * @return allocated string containing the name
229 */
gpio_bank_name(int bank)230 static char *gpio_bank_name(int bank)
231 {
232 char *name;
233
234 name = malloc(3);
235 if (name) {
236 name[0] = 'P';
237 name[1] = 'A' + bank;
238 name[2] = '\0';
239 }
240
241 return name;
242 }
243
gpio_sunxi_probe(struct udevice * dev)244 static int gpio_sunxi_probe(struct udevice *dev)
245 {
246 struct sunxi_gpio_plat *plat = dev_get_plat(dev);
247 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
248
249 /* Tell the uclass how many GPIOs we have */
250 if (plat) {
251 uc_priv->gpio_count = plat->gpio_count;
252 uc_priv->bank_name = plat->bank_name;
253 }
254
255 return 0;
256 }
257
258 struct sunxi_gpio_soc_data {
259 int start;
260 int no_banks;
261 };
262
263 /**
264 * We have a top-level GPIO device with no actual GPIOs. It has a child
265 * device for each Sunxi bank.
266 */
gpio_sunxi_bind(struct udevice * parent)267 static int gpio_sunxi_bind(struct udevice *parent)
268 {
269 struct sunxi_gpio_soc_data *soc_data =
270 (struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
271 struct sunxi_gpio_plat *plat = dev_get_plat(parent);
272 struct sunxi_gpio_reg *ctlr;
273 int bank, ret;
274
275 /* If this is a child device, there is nothing to do here */
276 if (plat)
277 return 0;
278
279 ctlr = dev_read_addr_ptr(parent);
280 for (bank = 0; bank < soc_data->no_banks; bank++) {
281 struct sunxi_gpio_plat *plat;
282 struct udevice *dev;
283
284 plat = calloc(1, sizeof(*plat));
285 if (!plat)
286 return -ENOMEM;
287 plat->regs = &ctlr->gpio_bank[bank];
288 plat->bank_name = gpio_bank_name(soc_data->start + bank);
289 plat->gpio_count = SUNXI_GPIOS_PER_BANK;
290
291 ret = device_bind(parent, parent->driver, plat->bank_name, plat,
292 dev_ofnode(parent), &dev);
293 if (ret)
294 return ret;
295 }
296
297 return 0;
298 }
299
300 static const struct sunxi_gpio_soc_data soc_data_a_all = {
301 .start = 0,
302 .no_banks = SUNXI_GPIO_BANKS,
303 };
304
305 static const struct sunxi_gpio_soc_data soc_data_l_1 = {
306 .start = 'L' - 'A',
307 .no_banks = 1,
308 };
309
310 static const struct sunxi_gpio_soc_data soc_data_l_2 = {
311 .start = 'L' - 'A',
312 .no_banks = 2,
313 };
314
315 static const struct sunxi_gpio_soc_data soc_data_l_3 = {
316 .start = 'L' - 'A',
317 .no_banks = 3,
318 };
319
320 #define ID(_compat_, _soc_data_) \
321 { .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
322
323 static const struct udevice_id sunxi_gpio_ids[] = {
324 ID("allwinner,sun4i-a10-pinctrl", a_all),
325 ID("allwinner,sun5i-a10s-pinctrl", a_all),
326 ID("allwinner,sun5i-a13-pinctrl", a_all),
327 ID("allwinner,sun50i-h5-pinctrl", a_all),
328 ID("allwinner,sun6i-a31-pinctrl", a_all),
329 ID("allwinner,sun6i-a31s-pinctrl", a_all),
330 ID("allwinner,sun7i-a20-pinctrl", a_all),
331 ID("allwinner,sun8i-a23-pinctrl", a_all),
332 ID("allwinner,sun8i-a33-pinctrl", a_all),
333 ID("allwinner,sun8i-a83t-pinctrl", a_all),
334 ID("allwinner,sun8i-h3-pinctrl", a_all),
335 ID("allwinner,sun8i-r40-pinctrl", a_all),
336 ID("allwinner,sun8i-v3-pinctrl", a_all),
337 ID("allwinner,sun8i-v3s-pinctrl", a_all),
338 ID("allwinner,sun9i-a80-pinctrl", a_all),
339 ID("allwinner,sun50i-a64-pinctrl", a_all),
340 ID("allwinner,sun50i-h6-pinctrl", a_all),
341 ID("allwinner,sun50i-h616-pinctrl", a_all),
342 ID("allwinner,sun6i-a31-r-pinctrl", l_2),
343 ID("allwinner,sun8i-a23-r-pinctrl", l_1),
344 ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
345 ID("allwinner,sun8i-h3-r-pinctrl", l_1),
346 ID("allwinner,sun9i-a80-r-pinctrl", l_3),
347 ID("allwinner,sun50i-a64-r-pinctrl", l_1),
348 ID("allwinner,sun50i-h6-r-pinctrl", l_2),
349 ID("allwinner,sun50i-h616-r-pinctrl", l_1),
350 { }
351 };
352
353 U_BOOT_DRIVER(gpio_sunxi) = {
354 .name = "gpio_sunxi",
355 .id = UCLASS_GPIO,
356 .ops = &gpio_sunxi_ops,
357 .of_match = sunxi_gpio_ids,
358 .bind = gpio_sunxi_bind,
359 .probe = gpio_sunxi_probe,
360 };
361 #endif /* DM_GPIO */
362