1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2017
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 *
6 * based on the ioep-fpga driver, which is
7 *
8 * (C) Copyright 2014
9 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <log.h>
15 #include <regmap.h>
16 #include <asm/gpio.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19
20 #include "ihs_fpga.h"
21
22 /**
23 * struct ihs_fpga_priv - Private data structure for IHS FPGA driver
24 * @map: Register map for the FPGA's own register space
25 * @reset_gpio: GPIO to start FPGA reconfiguration
26 * @done_gpio: GPOI to read the 'ready' status of the FPGA
27 */
28 struct ihs_fpga_priv {
29 struct regmap *map;
30 struct gpio_desc reset_gpio;
31 struct gpio_desc done_gpio;
32 };
33
34 /* Test pattern for reflection test */
35 const u16 REFLECTION_TESTPATTERN = 0xdead;
36 /* Delay (in ms) for each round in the reflection test */
37 const uint REFLECTION_TEST_DELAY = 100;
38 /* Maximum number of rounds in the reflection test */
39 const uint REFLECTION_TEST_ROUNDS = 5;
40 /* Delay (in ms) for each round waiting for the FPGA's done GPIO */
41 const uint FPGA_DONE_WAIT_DELAY = 100;
42 /* Maximum number of rounds for waiting for the FPGA's done GPIO */
43 const uint FPGA_DONE_WAIT_ROUND = 5;
44
45 /**
46 * enum pcb_video_type - Video type of the PCB
47 * @PCB_DVI_SL: Video type is DVI single-link
48 * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix)
49 * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix)
50 * @PCB_HDMI: Video type is HDMI
51 * @PCB_DP_1_2: Video type is DisplayPort 1.2
52 * @PCB_HDMI_2_0: Video type is HDMI 2.0
53 */
54 enum pcb_video_type {
55 PCB_DVI_SL,
56 PCB_DP_165MPIX,
57 PCB_DP_300MPIX,
58 PCB_HDMI,
59 PCB_DP_1_2,
60 PCB_HDMI_2_0,
61 };
62
63 /**
64 * enum pcb_transmission_type - Transmission type of the PCB
65 * @PCB_CAT_1G: Transmission type is 1G Ethernet
66 * @PCB_FIBER_3G: Transmission type is 3G Fiber
67 * @PCB_CAT_10G: Transmission type is 10G Ethernet
68 * @PCB_FIBER_10G: Transmission type is 10G Fiber
69 */
70 enum pcb_transmission_type {
71 PCB_CAT_1G,
72 PCB_FIBER_3G,
73 PCB_CAT_10G,
74 PCB_FIBER_10G,
75 };
76
77 /**
78 * enum carrier_speed - Speed of the FPGA's carrier
79 * @CARRIER_SPEED_1G: The carrier speed is 1G
80 * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G
81 * @CARRIER_SPEED_3G: The carrier speed is 3G
82 * @CARRIER_SPEED_10G: The carrier speed is 10G
83 */
84 enum carrier_speed {
85 CARRIER_SPEED_1G,
86 CARRIER_SPEED_3G,
87 CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
88 CARRIER_SPEED_10G,
89 };
90
91 /**
92 * enum ram_config - FPGA's RAM configuration
93 * @RAM_DDR2_32BIT_295MBPS: DDR2 32 bit at 295Mb/s
94 * @RAM_DDR3_32BIT_590MBPS: DDR3 32 bit at 590Mb/s
95 * @RAM_DDR3_48BIT_590MBPS: DDR3 48 bit at 590Mb/s
96 * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s
97 * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s
98 */
99 enum ram_config {
100 RAM_DDR2_32BIT_295MBPS,
101 RAM_DDR3_32BIT_590MBPS,
102 RAM_DDR3_48BIT_590MBPS,
103 RAM_DDR3_64BIT_1800MBPS,
104 RAM_DDR3_48BIT_1800MBPS,
105 };
106
107 /**
108 * enum sysclock - Speed of the FPGA's system clock
109 * @SYSCLK_147456: System clock is 147.456 MHz
110 */
111 enum sysclock {
112 SYSCLK_147456,
113 };
114
115 /**
116 * struct fpga_versions - Data read from the versions register
117 * @video_channel: Is the FPGA for a video channel (true) or main
118 * channel (false) device?
119 * @con_side: Is the FPGA for a CON (true) or a CPU (false) device?
120 * @pcb_video_type: Defines for whch video type the FPGA is configured
121 * @pcb_transmission_type: Defines for which transmission type the FPGA is
122 * configured
123 * @hw_version: Hardware version of the FPGA
124 */
125 struct fpga_versions {
126 bool video_channel;
127 bool con_side;
128 enum pcb_video_type pcb_video_type;
129 enum pcb_transmission_type pcb_transmission_type;
130 unsigned int hw_version;
131 };
132
133 /**
134 * struct fpga_features - Data read from the features register
135 * @video_channels: Number of video channels supported
136 * @carriers: Number of carrier channels supported
137 * @carrier_speed: Speed of carriers
138 * @ram_config: RAM configuration of FPGA
139 * @sysclock: System clock speed of FPGA
140 * @pcm_tx: Support for PCM transmission
141 * @pcm_rx: Support for PCM reception
142 * @spdif_tx: Support for SPDIF audio transmission
143 * @spdif_rx: Support for SPDIF audio reception
144 * @usb2: Support for transparent USB2.0
145 * @rs232: Support for bidirectional RS232
146 * @compression_type1: Support for compression type 1
147 * @compression_type2: Support for compression type 2
148 * @compression_type3: Support for compression type 3
149 * @interlace: Support for interlace image formats
150 * @osd: Support for a OSD
151 * @compression_pipes: Number of compression pipes supported
152 */
153 struct fpga_features {
154 u8 video_channels;
155 u8 carriers;
156 enum carrier_speed carrier_speed;
157 enum ram_config ram_config;
158 enum sysclock sysclock;
159 bool pcm_tx;
160 bool pcm_rx;
161 bool spdif_tx;
162 bool spdif_rx;
163 bool usb2;
164 bool rs232;
165 bool compression_type1;
166 bool compression_type2;
167 bool compression_type3;
168 bool interlace;
169 bool osd;
170 bool compression_pipes;
171 };
172
173 #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
174
175 /**
176 * get_versions() - Fill structure with info from version register.
177 * @dev: FPGA device to be queried for information
178 * @versions: Pointer to the structure to fill with information from the
179 * versions register
180 * Return: 0
181 */
get_versions(struct udevice * dev,struct fpga_versions * versions)182 static int get_versions(struct udevice *dev, struct fpga_versions *versions)
183 {
184 struct ihs_fpga_priv *priv = dev_get_priv(dev);
185 enum {
186 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
187 VERSIONS_FPGA_CON_SIDE = BIT(13),
188 VERSIONS_FPGA_SC = BIT(14),
189 VERSIONS_PCB_CON = BIT(9),
190 VERSIONS_PCB_SC = BIT(8),
191 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
192 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
193 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
194 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
195 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
196 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
197 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
198 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
199 VERSIONS_HW_VER_MASK = 0xf << 0,
200 };
201 u16 raw_versions;
202
203 memset(versions, 0, sizeof(struct fpga_versions));
204
205 ihs_fpga_get(priv->map, versions, &raw_versions);
206
207 versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
208 versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
209
210 switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
211 case VERSIONS_PCB_VIDEO_DP_1_2:
212 versions->pcb_video_type = PCB_DP_1_2;
213 break;
214
215 case VERSIONS_PCB_VIDEO_HDMI_2_0:
216 versions->pcb_video_type = PCB_HDMI_2_0;
217 break;
218 }
219
220 switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
221 case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
222 versions->pcb_transmission_type = PCB_FIBER_10G;
223 break;
224
225 case VERSIONS_PCB_TRANSMISSION_CAT_10G:
226 versions->pcb_transmission_type = PCB_CAT_10G;
227 break;
228
229 case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
230 versions->pcb_transmission_type = PCB_FIBER_3G;
231 break;
232
233 case VERSIONS_PCB_TRANSMISSION_CAT_1G:
234 versions->pcb_transmission_type = PCB_CAT_1G;
235 break;
236 }
237
238 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
239
240 return 0;
241 }
242
243 /**
244 * get_features() - Fill structure with info from features register.
245 * @dev: FPGA device to be queried for information
246 * @features: Pointer to the structure to fill with information from the
247 * features register
248 * Return: 0
249 */
get_features(struct udevice * dev,struct fpga_features * features)250 static int get_features(struct udevice *dev, struct fpga_features *features)
251 {
252 struct ihs_fpga_priv *priv = dev_get_priv(dev);
253 enum {
254 FEATURE_SPDIF_RX = BIT(15),
255 FEATURE_SPDIF_TX = BIT(14),
256 FEATURE_PCM_RX = BIT(13),
257 FEATURE_PCM_TX = BIT(12),
258 FEATURE_RAM_MASK = GENMASK(11, 8),
259 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
260 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
261 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
262 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
263 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
264 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
265 FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
266 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
267 FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
268 FEATURE_CARRIERS_MASK = GENMASK(5, 4),
269 FEATURE_CARRIERS_0 = 0x0 << 4,
270 FEATURE_CARRIERS_1 = 0x1 << 4,
271 FEATURE_CARRIERS_2 = 0x2 << 4,
272 FEATURE_CARRIERS_4 = 0x3 << 4,
273 FEATURE_USB2 = BIT(3),
274 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
275 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
276 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
277 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
278 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
279 };
280
281 enum {
282 EXT_FEATURE_OSD = BIT(15),
283 EXT_FEATURE_ETHERNET = BIT(9),
284 EXT_FEATURE_INTERLACE = BIT(8),
285 EXT_FEATURE_RS232 = BIT(7),
286 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
287 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
288 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
289 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
290 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
291 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
292 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
293 };
294
295 u16 raw_features;
296 u16 raw_extended_features;
297
298 memset(features, 0, sizeof(struct fpga_features));
299
300 ihs_fpga_get(priv->map, features, &raw_features);
301 ihs_fpga_get(priv->map, extended_features, &raw_extended_features);
302
303 switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
304 case FEATURE_VIDEOCHANNELS_0:
305 features->video_channels = 0;
306 break;
307
308 case FEATURE_VIDEOCHANNELS_1:
309 features->video_channels = 1;
310 break;
311
312 case FEATURE_VIDEOCHANNELS_1_1:
313 case FEATURE_VIDEOCHANNELS_2:
314 features->video_channels = 2;
315 break;
316 };
317
318 switch (raw_features & FEATURE_CARRIERS_MASK) {
319 case FEATURE_CARRIERS_0:
320 features->carriers = 0;
321 break;
322
323 case FEATURE_CARRIERS_1:
324 features->carriers = 1;
325 break;
326
327 case FEATURE_CARRIERS_2:
328 features->carriers = 2;
329 break;
330
331 case FEATURE_CARRIERS_4:
332 features->carriers = 4;
333 break;
334 }
335
336 switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
337 case FEATURE_CARRIER_SPEED_1G:
338 features->carrier_speed = CARRIER_SPEED_1G;
339 break;
340 case FEATURE_CARRIER_SPEED_2_5G:
341 features->carrier_speed = CARRIER_SPEED_2_5G;
342 break;
343 case FEATURE_CARRIER_SPEED_10G:
344 features->carrier_speed = CARRIER_SPEED_10G;
345 break;
346 }
347
348 switch (raw_features & FEATURE_RAM_MASK) {
349 case FEATURE_RAM_DDR2_32BIT_295MBPS:
350 features->ram_config = RAM_DDR2_32BIT_295MBPS;
351 break;
352
353 case FEATURE_RAM_DDR3_32BIT_590MBPS:
354 features->ram_config = RAM_DDR3_32BIT_590MBPS;
355 break;
356
357 case FEATURE_RAM_DDR3_48BIT_590MBPS:
358 features->ram_config = RAM_DDR3_48BIT_590MBPS;
359 break;
360
361 case FEATURE_RAM_DDR3_64BIT_1800MBPS:
362 features->ram_config = RAM_DDR3_64BIT_1800MBPS;
363 break;
364
365 case FEATURE_RAM_DDR3_48BIT_1800MBPS:
366 features->ram_config = RAM_DDR3_48BIT_1800MBPS;
367 break;
368 }
369
370 features->pcm_tx = raw_features & FEATURE_PCM_TX;
371 features->pcm_rx = raw_features & FEATURE_PCM_RX;
372 features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
373 features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
374 features->usb2 = raw_features & FEATURE_USB2;
375 features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
376 features->compression_type1 = raw_extended_features &
377 EXT_FEATURE_COMPRESSION_TYPE1;
378 features->compression_type2 = raw_extended_features &
379 EXT_FEATURE_COMPRESSION_TYPE2;
380 features->compression_type3 = raw_extended_features &
381 EXT_FEATURE_COMPRESSION_TYPE3;
382 features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
383 features->osd = raw_extended_features & EXT_FEATURE_OSD;
384 features->compression_pipes = raw_extended_features &
385 EXT_FEATURE_COMPRESSION_PERF_MASK;
386
387 return 0;
388 }
389
390 #else
391
392 /**
393 * get_versions() - Fill structure with info from version register.
394 * @fpga: Identifier of the FPGA device to be queried for information
395 * @versions: Pointer to the structure to fill with information from the
396 * versions register
397 *
398 * This is the legacy version and should be considered deprecated for new
399 * devices.
400 *
401 * Return: 0
402 */
get_versions(unsigned int fpga,struct fpga_versions * versions)403 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
404 {
405 enum {
406 /* HW version encoding is a mess, leave it for the moment */
407 VERSIONS_HW_VER_MASK = 0xf << 0,
408 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
409 VERSIONS_SFP = BIT(5),
410 VERSIONS_VIDEO_MASK = 0x7 << 6,
411 VERSIONS_VIDEO_DVI = 0x0 << 6,
412 VERSIONS_VIDEO_DP_165 = 0x1 << 6,
413 VERSIONS_VIDEO_DP_300 = 0x2 << 6,
414 VERSIONS_VIDEO_HDMI = 0x3 << 6,
415 VERSIONS_UT_MASK = 0xf << 12,
416 VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
417 VERSIONS_UT_MAIN_USER = 0x1 << 12,
418 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
419 VERSIONS_UT_VIDEO_USER = 0x3 << 12,
420 };
421 u16 raw_versions;
422
423 memset(versions, 0, sizeof(struct fpga_versions));
424
425 FPGA_GET_REG(fpga, versions, &raw_versions);
426
427 switch (raw_versions & VERSIONS_UT_MASK) {
428 case VERSIONS_UT_MAIN_SERVER:
429 versions->video_channel = false;
430 versions->con_side = false;
431 break;
432
433 case VERSIONS_UT_MAIN_USER:
434 versions->video_channel = false;
435 versions->con_side = true;
436 break;
437
438 case VERSIONS_UT_VIDEO_SERVER:
439 versions->video_channel = true;
440 versions->con_side = false;
441 break;
442
443 case VERSIONS_UT_VIDEO_USER:
444 versions->video_channel = true;
445 versions->con_side = true;
446 break;
447 }
448
449 switch (raw_versions & VERSIONS_VIDEO_MASK) {
450 case VERSIONS_VIDEO_DVI:
451 versions->pcb_video_type = PCB_DVI_SL;
452 break;
453
454 case VERSIONS_VIDEO_DP_165:
455 versions->pcb_video_type = PCB_DP_165MPIX;
456 break;
457
458 case VERSIONS_VIDEO_DP_300:
459 versions->pcb_video_type = PCB_DP_300MPIX;
460 break;
461
462 case VERSIONS_VIDEO_HDMI:
463 versions->pcb_video_type = PCB_HDMI;
464 break;
465 }
466
467 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
468
469 if (raw_versions & VERSIONS_SFP)
470 versions->pcb_transmission_type = PCB_FIBER_3G;
471 else
472 versions->pcb_transmission_type = PCB_CAT_1G;
473
474 return 0;
475 }
476
477 /**
478 * get_features() - Fill structure with info from features register.
479 * @fpga: Identifier of the FPGA device to be queried for information
480 * @features: Pointer to the structure to fill with information from the
481 * features register
482 *
483 * This is the legacy version and should be considered deprecated for new
484 * devices.
485 *
486 * Return: 0
487 */
get_features(unsigned int fpga,struct fpga_features * features)488 static int get_features(unsigned int fpga, struct fpga_features *features)
489 {
490 enum {
491 FEATURE_CARRIER_SPEED_2_5 = BIT(4),
492 FEATURE_RAM_MASK = 0x7 << 5,
493 FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
494 FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
495 FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
496 FEATURE_PCM_AUDIO_TX = BIT(9),
497 FEATURE_PCM_AUDIO_RX = BIT(10),
498 FEATURE_OSD = BIT(11),
499 FEATURE_USB20 = BIT(12),
500 FEATURE_COMPRESSION_MASK = 7 << 13,
501 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
502 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
503 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
504 };
505
506 enum {
507 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
508 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
509 EXTENDED_FEATURE_RS232 = BIT(2),
510 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
511 EXTENDED_FEATURE_INTERLACE = BIT(4),
512 };
513
514 u16 raw_features;
515 u16 raw_extended_features;
516
517 memset(features, 0, sizeof(struct fpga_features));
518
519 FPGA_GET_REG(fpga, fpga_features, &raw_features);
520 FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
521
522 features->video_channels = raw_features & 0x3;
523 features->carriers = (raw_features >> 2) & 0x3;
524
525 features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
526 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
527
528 switch (raw_features & FEATURE_RAM_MASK) {
529 case FEATURE_RAM_DDR2_32BIT:
530 features->ram_config = RAM_DDR2_32BIT_295MBPS;
531 break;
532
533 case FEATURE_RAM_DDR3_32BIT:
534 features->ram_config = RAM_DDR3_32BIT_590MBPS;
535 break;
536
537 case FEATURE_RAM_DDR3_48BIT:
538 features->ram_config = RAM_DDR3_48BIT_590MBPS;
539 break;
540 }
541
542 features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
543 features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
544 features->spdif_tx = raw_extended_features &
545 EXTENDED_FEATURE_SPDIF_AUDIO_TX;
546 features->spdif_rx = raw_extended_features &
547 EXTENDED_FEATURE_SPDIF_AUDIO_RX;
548
549 features->usb2 = raw_features & FEATURE_USB20;
550 features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
551
552 features->compression_type1 = false;
553 features->compression_type2 = false;
554 features->compression_type3 = false;
555 switch (raw_features & FEATURE_COMPRESSION_MASK) {
556 case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
557 features->compression_type3 = true;
558 /* fall-through */
559 case FEATURE_COMPRESSION_TYPE1_TYPE2:
560 features->compression_type2 = true;
561 /* fall-through */
562 case FEATURE_COMPRESSION_TYPE1:
563 features->compression_type1 = true;
564 break;
565 }
566
567 features->interlace = raw_extended_features &
568 EXTENDED_FEATURE_INTERLACE;
569 features->osd = raw_features & FEATURE_OSD;
570 features->compression_pipes = raw_extended_features &
571 EXTENDED_FEATURE_COMPRESSION_PIPES;
572
573 return 0;
574 }
575
576 #endif
577
578 /**
579 * fpga_print_info() - Print information about FPGA device
580 * @dev: FPGA device to print information about
581 */
fpga_print_info(struct udevice * dev)582 static void fpga_print_info(struct udevice *dev)
583 {
584 struct ihs_fpga_priv *priv = dev_get_priv(dev);
585 u16 fpga_version;
586 struct fpga_versions versions;
587 struct fpga_features features;
588
589 ihs_fpga_get(priv->map, fpga_version, &fpga_version);
590 get_versions(dev, &versions);
591 get_features(dev, &features);
592
593 if (versions.video_channel)
594 printf("Videochannel");
595 else
596 printf("Mainchannel");
597
598 if (versions.con_side)
599 printf(" User");
600 else
601 printf(" Server");
602
603 switch (versions.pcb_transmission_type) {
604 case PCB_CAT_1G:
605 case PCB_CAT_10G:
606 printf(" CAT");
607 break;
608 case PCB_FIBER_3G:
609 case PCB_FIBER_10G:
610 printf(" Fiber");
611 break;
612 };
613
614 switch (versions.pcb_video_type) {
615 case PCB_DVI_SL:
616 printf(" DVI,");
617 break;
618 case PCB_DP_165MPIX:
619 printf(" DP 165MPix/s,");
620 break;
621 case PCB_DP_300MPIX:
622 printf(" DP 300MPix/s,");
623 break;
624 case PCB_HDMI:
625 printf(" HDMI,");
626 break;
627 case PCB_DP_1_2:
628 printf(" DP 1.2,");
629 break;
630 case PCB_HDMI_2_0:
631 printf(" HDMI 2.0,");
632 break;
633 }
634
635 printf(" FPGA V %d.%02d\n features: ",
636 fpga_version / 100, fpga_version % 100);
637
638 if (!features.compression_type1 &&
639 !features.compression_type2 &&
640 !features.compression_type3)
641 printf("no compression, ");
642
643 if (features.compression_type1)
644 printf("type1, ");
645
646 if (features.compression_type2)
647 printf("type2, ");
648
649 if (features.compression_type3)
650 printf("type3, ");
651
652 printf("%sosd", features.osd ? "" : "no ");
653
654 if (features.pcm_rx && features.pcm_tx)
655 printf(", pcm rx+tx");
656 else if (features.pcm_rx)
657 printf(", pcm rx");
658 else if (features.pcm_tx)
659 printf(", pcm tx");
660
661 if (features.spdif_rx && features.spdif_tx)
662 printf(", spdif rx+tx");
663 else if (features.spdif_rx)
664 printf(", spdif rx");
665 else if (features.spdif_tx)
666 printf(", spdif tx");
667
668 puts(",\n ");
669
670 switch (features.sysclock) {
671 case SYSCLK_147456:
672 printf("clock 147.456 MHz");
673 break;
674 }
675
676 switch (features.ram_config) {
677 case RAM_DDR2_32BIT_295MBPS:
678 printf(", RAM 32 bit DDR2");
679 break;
680 case RAM_DDR3_32BIT_590MBPS:
681 printf(", RAM 32 bit DDR3");
682 break;
683 case RAM_DDR3_48BIT_590MBPS:
684 case RAM_DDR3_48BIT_1800MBPS:
685 printf(", RAM 48 bit DDR3");
686 break;
687 case RAM_DDR3_64BIT_1800MBPS:
688 printf(", RAM 64 bit DDR3");
689 break;
690 }
691
692 printf(", %d carrier(s)", features.carriers);
693
694 switch (features.carrier_speed) {
695 case CARRIER_SPEED_1G:
696 printf(", 1Gbit/s");
697 break;
698 case CARRIER_SPEED_3G:
699 printf(", 3Gbit/s");
700 break;
701 case CARRIER_SPEED_10G:
702 printf(", 10Gbit/s");
703 break;
704 }
705
706 printf(", %d video channel(s)\n", features.video_channels);
707 }
708
709 /**
710 * do_reflection_test() - Run reflection test on a FPGA device
711 * @dev: FPGA device to run reflection test on
712 *
713 * Return: 0 if reflection test succeeded, -ve on error
714 */
do_reflection_test(struct udevice * dev)715 static int do_reflection_test(struct udevice *dev)
716 {
717 struct ihs_fpga_priv *priv = dev_get_priv(dev);
718 int ctr = 0;
719
720 while (1) {
721 u16 val;
722
723 ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN);
724
725 ihs_fpga_get(priv->map, reflection_low, &val);
726 if (val == (~REFLECTION_TESTPATTERN & 0xffff))
727 return -EIO;
728
729 mdelay(REFLECTION_TEST_DELAY);
730 if (ctr++ > REFLECTION_TEST_ROUNDS)
731 return 0;
732 }
733 }
734
735 /**
736 * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device
737 * @dev: FPGA device whose done flag to wait for
738 *
739 * This function waits until it detects that the done-GPIO's value was changed
740 * to 1 by the FPGA, which indicates that the device is configured and ready to
741 * use.
742 *
743 * Return: 0 if done flag was detected, -ve on error
744 */
wait_for_fpga_done(struct udevice * dev)745 static int wait_for_fpga_done(struct udevice *dev)
746 {
747 struct ihs_fpga_priv *priv = dev_get_priv(dev);
748 int ctr = 0;
749 int done_val;
750
751 while (1) {
752 done_val = dm_gpio_get_value(&priv->done_gpio);
753 if (done_val < 0) {
754 debug("%s: Error while reading done-GPIO (err = %d)\n",
755 dev->name, done_val);
756 return done_val;
757 }
758
759 if (done_val)
760 return 0;
761
762 mdelay(FPGA_DONE_WAIT_DELAY);
763 if (ctr++ > FPGA_DONE_WAIT_ROUND) {
764 debug("%s: FPGA init failed (done not detected)\n",
765 dev->name);
766 return -EIO;
767 }
768 }
769 }
770
ihs_fpga_probe(struct udevice * dev)771 static int ihs_fpga_probe(struct udevice *dev)
772 {
773 struct ihs_fpga_priv *priv = dev_get_priv(dev);
774 int ret;
775
776 /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */
777
778 ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
779 if (ret) {
780 debug("%s: Could not initialize regmap (err = %d)",
781 dev->name, ret);
782 return ret;
783 }
784
785 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
786 GPIOD_IS_OUT);
787 if (ret) {
788 debug("%s: Could not get reset-GPIO (err = %d)\n",
789 dev->name, ret);
790 return ret;
791 }
792
793 if (!priv->reset_gpio.dev) {
794 debug("%s: Could not get reset-GPIO\n", dev->name);
795 return -ENOENT;
796 }
797
798 ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
799 GPIOD_IS_IN);
800 if (ret) {
801 debug("%s: Could not get done-GPIO (err = %d)\n",
802 dev->name, ret);
803 return ret;
804 }
805
806 if (!priv->done_gpio.dev) {
807 debug("%s: Could not get done-GPIO\n", dev->name);
808 return -ENOENT;
809 }
810
811 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
812 if (ret) {
813 debug("%s: Error while setting reset-GPIO (err = %d)\n",
814 dev->name, ret);
815 return ret;
816 }
817
818 /* If FPGA already runs, don't initialize again */
819 if (do_reflection_test(dev))
820 goto reflection_ok;
821
822 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
823 if (ret) {
824 debug("%s: Error while setting reset-GPIO (err = %d)\n",
825 dev->name, ret);
826 return ret;
827 }
828
829 ret = wait_for_fpga_done(dev);
830 if (ret) {
831 debug("%s: Error while waiting for FPGA done (err = %d)\n",
832 dev->name, ret);
833 return ret;
834 }
835
836 udelay(10);
837
838 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
839 if (ret) {
840 debug("%s: Error while setting reset-GPIO (err = %d)\n",
841 dev->name, ret);
842 return ret;
843 }
844
845 if (!do_reflection_test(dev)) {
846 debug("%s: Reflection test FAILED\n", dev->name);
847 return -EIO;
848 }
849
850 reflection_ok:
851 printf("%s: Reflection test passed.\n", dev->name);
852
853 fpga_print_info(dev);
854
855 return 0;
856 }
857
858 static const struct udevice_id ihs_fpga_ids[] = {
859 { .compatible = "gdsys,iocon_fpga" },
860 { .compatible = "gdsys,iocpu_fpga" },
861 { }
862 };
863
864 U_BOOT_DRIVER(ihs_fpga_bus) = {
865 .name = "ihs_fpga_bus",
866 .id = UCLASS_MISC,
867 .of_match = ihs_fpga_ids,
868 .probe = ihs_fpga_probe,
869 .priv_auto = sizeof(struct ihs_fpga_priv),
870 };
871