1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2020 NXP
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <dm.h>
9 #include <dm/lists.h>
10 #include <dm/root.h>
11 #include <dm/device-internal.h>
12 #include <asm/arch/s400_api.h>
13 #include <asm/arch/imx-regs.h>
14 #include <linux/iopoll.h>
15 #include <misc.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct imx8ulp_mu {
20 struct mu_type *base;
21 };
22
23 #define MU_SR_TE0_MASK BIT(0)
24 #define MU_SR_RF0_MASK BIT(0)
25 #define MU_TR_COUNT 4
26 #define MU_RR_COUNT 4
27
mu_hal_init(ulong base)28 void mu_hal_init(ulong base)
29 {
30 struct mu_type *mu_base = (struct mu_type *)base;
31
32 writel(0, &mu_base->tcr);
33 writel(0, &mu_base->rcr);
34 }
35
mu_hal_sendmsg(ulong base,u32 reg_index,u32 msg)36 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
37 {
38 struct mu_type *mu_base = (struct mu_type *)base;
39 u32 mask = MU_SR_TE0_MASK << reg_index;
40 u32 val;
41 int ret;
42
43 assert(reg_index < MU_TR_COUNT);
44
45 debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
46
47 /* Wait TX register to be empty. */
48 ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
49 if (ret < 0) {
50 debug("%s timeout\n", __func__);
51 return -ETIMEDOUT;
52 }
53
54 debug("tr[%d] 0x%x\n", reg_index, msg);
55
56 writel(msg, &mu_base->tr[reg_index]);
57
58 return 0;
59 }
60
mu_hal_receivemsg(ulong base,u32 reg_index,u32 * msg)61 int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
62 {
63 struct mu_type *mu_base = (struct mu_type *)base;
64 u32 mask = MU_SR_RF0_MASK << reg_index;
65 u32 val;
66 int ret;
67
68 assert(reg_index < MU_TR_COUNT);
69
70 debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
71
72 /* Wait RX register to be full. */
73 ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
74 if (ret < 0) {
75 debug("%s timeout\n", __func__);
76 return -ETIMEDOUT;
77 }
78
79 *msg = readl(&mu_base->rr[reg_index]);
80
81 debug("rr[%d] 0x%x\n", reg_index, *msg);
82
83 return 0;
84 }
85
imx8ulp_mu_read(struct mu_type * base,void * data)86 static int imx8ulp_mu_read(struct mu_type *base, void *data)
87 {
88 struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
89 int ret;
90 u8 count = 0;
91
92 if (!msg)
93 return -EINVAL;
94
95 /* Read first word */
96 ret = mu_hal_receivemsg((ulong)base, 0, (u32 *)msg);
97 if (ret)
98 return ret;
99 count++;
100
101 /* Check size */
102 if (msg->size > S400_MAX_MSG) {
103 *((u32 *)msg) = 0;
104 return -EINVAL;
105 }
106
107 /* Read remaining words */
108 while (count < msg->size) {
109 ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
110 &msg->data[count - 1]);
111 if (ret)
112 return ret;
113 count++;
114 }
115
116 return 0;
117 }
118
imx8ulp_mu_write(struct mu_type * base,void * data)119 static int imx8ulp_mu_write(struct mu_type *base, void *data)
120 {
121 struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
122 int ret;
123 u8 count = 0;
124
125 if (!msg)
126 return -EINVAL;
127
128 /* Check size */
129 if (msg->size > S400_MAX_MSG)
130 return -EINVAL;
131
132 /* Write first word */
133 ret = mu_hal_sendmsg((ulong)base, 0, *((u32 *)msg));
134 if (ret)
135 return ret;
136 count++;
137
138 /* Write remaining words */
139 while (count < msg->size) {
140 ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
141 msg->data[count - 1]);
142 if (ret)
143 return ret;
144 count++;
145 }
146
147 return 0;
148 }
149
150 /*
151 * Note the function prototype use msgid as the 2nd parameter, here
152 * we take it as no_resp.
153 */
imx8ulp_mu_call(struct udevice * dev,int no_resp,void * tx_msg,int tx_size,void * rx_msg,int rx_size)154 static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
155 int tx_size, void *rx_msg, int rx_size)
156 {
157 struct imx8ulp_mu *priv = dev_get_priv(dev);
158 u32 result;
159 int ret;
160
161 /* Expect tx_msg, rx_msg are the same value */
162 if (rx_msg && tx_msg != rx_msg)
163 printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
164
165 ret = imx8ulp_mu_write(priv->base, tx_msg);
166 if (ret)
167 return ret;
168 if (!no_resp) {
169 ret = imx8ulp_mu_read(priv->base, rx_msg);
170 if (ret)
171 return ret;
172 }
173
174 result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
175 if ((result & 0xff) == 0xd6)
176 return 0;
177
178 return -EIO;
179 }
180
imx8ulp_mu_probe(struct udevice * dev)181 static int imx8ulp_mu_probe(struct udevice *dev)
182 {
183 struct imx8ulp_mu *priv = dev_get_priv(dev);
184 fdt_addr_t addr;
185
186 debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
187
188 addr = devfdt_get_addr(dev);
189 if (addr == FDT_ADDR_T_NONE)
190 return -EINVAL;
191
192 priv->base = (struct mu_type *)addr;
193
194 debug("mu base 0x%lx\n", (ulong)priv->base);
195
196 /* U-Boot not enable interrupts, so need to enable RX interrupts */
197 mu_hal_init((ulong)priv->base);
198
199 gd->arch.s400_dev = dev;
200
201 return 0;
202 }
203
imx8ulp_mu_remove(struct udevice * dev)204 static int imx8ulp_mu_remove(struct udevice *dev)
205 {
206 return 0;
207 }
208
imx8ulp_mu_bind(struct udevice * dev)209 static int imx8ulp_mu_bind(struct udevice *dev)
210 {
211 debug("%s(dev=%p)\n", __func__, dev);
212
213 return 0;
214 }
215
216 static struct misc_ops imx8ulp_mu_ops = {
217 .call = imx8ulp_mu_call,
218 };
219
220 static const struct udevice_id imx8ulp_mu_ids[] = {
221 { .compatible = "fsl,imx8ulp-mu" },
222 { }
223 };
224
225 U_BOOT_DRIVER(imx8ulp_mu) = {
226 .name = "imx8ulp_mu",
227 .id = UCLASS_MISC,
228 .of_match = imx8ulp_mu_ids,
229 .probe = imx8ulp_mu_probe,
230 .bind = imx8ulp_mu_bind,
231 .remove = imx8ulp_mu_remove,
232 .ops = &imx8ulp_mu_ops,
233 .priv_auto = sizeof(struct imx8ulp_mu),
234 };
235