1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019-2021 NXP
5 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <cpu_func.h>
16 #include <errno.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <part.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <dm.h>
27 #include <dm/device_compat.h>
28 #include <linux/bitops.h>
29 #include <linux/delay.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32 #include <sdhci.h>
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 struct fsl_esdhc {
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 char reserved1[8]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddrl; /* ADMA system address low register */
59 uint adsaddrh; /* ADMA system address high register */
60 char reserved2[156];
61 uint hostver; /* Host controller version register */
62 char reserved3[4]; /* reserved */
63 uint dmaerraddr; /* DMA error address register */
64 char reserved4[4]; /* reserved */
65 uint dmaerrattr; /* DMA error attribute register */
66 char reserved5[4]; /* reserved */
67 uint hostcapblt2; /* Host controller capabilities register 2 */
68 char reserved6[8]; /* reserved */
69 uint tbctl; /* Tuning block control register */
70 char reserved7[32]; /* reserved */
71 uint sdclkctl; /* SD clock control register */
72 uint sdtimingctl; /* SD timing control register */
73 char reserved8[20]; /* reserved */
74 uint dllcfg0; /* DLL config 0 register */
75 uint dllcfg1; /* DLL config 1 register */
76 char reserved9[8]; /* reserved */
77 uint dllstat0; /* DLL status 0 register */
78 char reserved10[664];/* reserved */
79 uint esdhcctl; /* eSDHC control register */
80 };
81
82 struct fsl_esdhc_plat {
83 struct mmc_config cfg;
84 struct mmc mmc;
85 };
86
87 /**
88 * struct fsl_esdhc_priv
89 *
90 * @esdhc_regs: registers of the sdhc controller
91 * @sdhc_clk: Current clk of the sdhc controller
92 * @bus_width: bus width, 1bit, 4bit or 8bit
93 * @cfg: mmc config
94 * @mmc: mmc
95 * Following is used when Driver Model is enabled for MMC
96 * @dev: pointer for the device
97 * @cd_gpio: gpio for card detection
98 * @wp_gpio: gpio for write protection
99 */
100 struct fsl_esdhc_priv {
101 struct fsl_esdhc *esdhc_regs;
102 unsigned int sdhc_clk;
103 bool is_sdhc_per_clk;
104 unsigned int clock;
105 #if !CONFIG_IS_ENABLED(DM_MMC)
106 struct mmc *mmc;
107 #endif
108 struct udevice *dev;
109 struct sdhci_adma_desc *adma_desc_table;
110 dma_addr_t dma_addr;
111 };
112
113 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)114 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
115 {
116 uint xfertyp = 0;
117
118 if (data) {
119 xfertyp |= XFERTYP_DPSEL;
120 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
121 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
122 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
123 xfertyp |= XFERTYP_DMAEN;
124 if (data->blocks > 1) {
125 xfertyp |= XFERTYP_MSBSEL;
126 xfertyp |= XFERTYP_BCEN;
127 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
128 xfertyp |= XFERTYP_AC12EN;
129 }
130
131 if (data->flags & MMC_DATA_READ)
132 xfertyp |= XFERTYP_DTDSEL;
133 }
134
135 if (cmd->resp_type & MMC_RSP_CRC)
136 xfertyp |= XFERTYP_CCCEN;
137 if (cmd->resp_type & MMC_RSP_OPCODE)
138 xfertyp |= XFERTYP_CICEN;
139 if (cmd->resp_type & MMC_RSP_136)
140 xfertyp |= XFERTYP_RSPTYP_136;
141 else if (cmd->resp_type & MMC_RSP_BUSY)
142 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
143 else if (cmd->resp_type & MMC_RSP_PRESENT)
144 xfertyp |= XFERTYP_RSPTYP_48;
145
146 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
147 xfertyp |= XFERTYP_CMDTYP_ABORT;
148
149 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
150 }
151
152 /*
153 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
154 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)155 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
156 struct mmc_data *data)
157 {
158 struct fsl_esdhc *regs = priv->esdhc_regs;
159 uint blocks;
160 char *buffer;
161 uint databuf;
162 uint size;
163 uint irqstat;
164 ulong start;
165
166 if (data->flags & MMC_DATA_READ) {
167 blocks = data->blocks;
168 buffer = data->dest;
169 while (blocks) {
170 start = get_timer(0);
171 size = data->blocksize;
172 irqstat = esdhc_read32(®s->irqstat);
173 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
174 if (get_timer(start) > PIO_TIMEOUT) {
175 printf("\nData Read Failed in PIO Mode.");
176 return;
177 }
178 }
179 while (size && (!(irqstat & IRQSTAT_TC))) {
180 udelay(100); /* Wait before last byte transfer complete */
181 irqstat = esdhc_read32(®s->irqstat);
182 databuf = in_le32(®s->datport);
183 *((uint *)buffer) = databuf;
184 buffer += 4;
185 size -= 4;
186 }
187 blocks--;
188 }
189 } else {
190 blocks = data->blocks;
191 buffer = (char *)data->src;
192 while (blocks) {
193 start = get_timer(0);
194 size = data->blocksize;
195 irqstat = esdhc_read32(®s->irqstat);
196 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
197 if (get_timer(start) > PIO_TIMEOUT) {
198 printf("\nData Write Failed in PIO Mode.");
199 return;
200 }
201 }
202 while (size && (!(irqstat & IRQSTAT_TC))) {
203 udelay(100); /* Wait before last byte transfer complete */
204 databuf = *((uint *)buffer);
205 buffer += 4;
206 size -= 4;
207 irqstat = esdhc_read32(®s->irqstat);
208 out_le32(®s->datport, databuf);
209 }
210 blocks--;
211 }
212 }
213 }
214
esdhc_setup_watermark_level(struct fsl_esdhc_priv * priv,struct mmc_data * data)215 static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
216 struct mmc_data *data)
217 {
218 struct fsl_esdhc *regs = priv->esdhc_regs;
219 uint wml_value = data->blocksize / 4;
220
221 if (data->flags & MMC_DATA_READ) {
222 if (wml_value > WML_RD_WML_MAX)
223 wml_value = WML_RD_WML_MAX_VAL;
224
225 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
226 } else {
227 if (wml_value > WML_WR_WML_MAX)
228 wml_value = WML_WR_WML_MAX_VAL;
229
230 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
231 wml_value << 16);
232 }
233 }
234
esdhc_setup_dma(struct fsl_esdhc_priv * priv,struct mmc_data * data)235 static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
236 {
237 uint trans_bytes = data->blocksize * data->blocks;
238 struct fsl_esdhc *regs = priv->esdhc_regs;
239 phys_addr_t adma_addr;
240 void *buf;
241
242 if (data->flags & MMC_DATA_WRITE)
243 buf = (void *)data->src;
244 else
245 buf = data->dest;
246
247 priv->dma_addr = dma_map_single(buf, trans_bytes,
248 mmc_get_dma_dir(data));
249
250 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
251 priv->adma_desc_table) {
252 debug("Using ADMA2\n");
253 /* prefer ADMA2 if it is available */
254 sdhci_prepare_adma_table(priv->adma_desc_table, data,
255 priv->dma_addr);
256
257 adma_addr = virt_to_phys(priv->adma_desc_table);
258 esdhc_write32(®s->adsaddrl, lower_32_bits(adma_addr));
259 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
260 esdhc_write32(®s->adsaddrh, upper_32_bits(adma_addr));
261 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
262 PROCTL_DMAS_ADMA2);
263 } else {
264 debug("Using SDMA\n");
265 if (upper_32_bits(priv->dma_addr))
266 printf("Cannot use 64 bit addresses with SDMA\n");
267 esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr));
268 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
269 PROCTL_DMAS_SDMA);
270 }
271
272 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
273 }
274
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)275 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
276 struct mmc_data *data)
277 {
278 int timeout;
279 bool is_write = data->flags & MMC_DATA_WRITE;
280 struct fsl_esdhc *regs = priv->esdhc_regs;
281
282 if (is_write && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
283 printf("Can not write to locked SD card.\n");
284 return -EINVAL;
285 }
286
287 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
288 esdhc_setup_watermark_level(priv, data);
289 else
290 esdhc_setup_dma(priv, data);
291
292 /* Calculate the timeout period for data transactions */
293 /*
294 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
295 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
296 * So, Number of SD Clock cycles for 0.25sec should be minimum
297 * (SD Clock/sec * 0.25 sec) SD Clock cycles
298 * = (mmc->clock * 1/4) SD Clock cycles
299 * As 1) >= 2)
300 * => (2^(timeout+13)) >= mmc->clock * 1/4
301 * Taking log2 both the sides
302 * => timeout + 13 >= log2(mmc->clock/4)
303 * Rounding up to next power of 2
304 * => timeout + 13 = log2(mmc->clock/4) + 1
305 * => timeout + 13 = fls(mmc->clock/4)
306 *
307 * However, the MMC spec "It is strongly recommended for hosts to
308 * implement more than 500ms timeout value even if the card
309 * indicates the 250ms maximum busy length." Even the previous
310 * value of 300ms is known to be insufficient for some cards.
311 * So, we use
312 * => timeout + 13 = fls(mmc->clock/2)
313 */
314 timeout = fls(mmc->clock/2);
315 timeout -= 13;
316
317 if (timeout > 14)
318 timeout = 14;
319
320 if (timeout < 0)
321 timeout = 0;
322
323 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
324 (timeout == 4 || timeout == 8 || timeout == 12))
325 timeout++;
326
327 if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
328 timeout = 0xE;
329
330 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
331
332 return 0;
333 }
334
335 /*
336 * Sends a command out on the bus. Takes the mmc pointer,
337 * a command pointer, and an optional data pointer.
338 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)339 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
340 struct mmc_cmd *cmd, struct mmc_data *data)
341 {
342 int err = 0;
343 uint xfertyp;
344 uint irqstat;
345 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
346 struct fsl_esdhc *regs = priv->esdhc_regs;
347 unsigned long start;
348
349 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
350 cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
351 return 0;
352
353 esdhc_write32(®s->irqstat, -1);
354
355 sync();
356
357 /* Wait for the bus to be idle */
358 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
359 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
360 ;
361
362 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
363 ;
364
365 /* Set up for a data transfer if we have one */
366 if (data) {
367 err = esdhc_setup_data(priv, mmc, data);
368 if(err)
369 return err;
370 }
371
372 /* Figure out the transfer arguments */
373 xfertyp = esdhc_xfertyp(cmd, data);
374
375 /* Mask all irqs */
376 esdhc_write32(®s->irqsigen, 0);
377
378 /* Send the command */
379 esdhc_write32(®s->cmdarg, cmd->cmdarg);
380 esdhc_write32(®s->xfertyp, xfertyp);
381
382 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
383 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
384 flags = IRQSTAT_BRR;
385
386 /* Wait for the command to complete */
387 start = get_timer(0);
388 while (!(esdhc_read32(®s->irqstat) & flags)) {
389 if (get_timer(start) > 1000) {
390 err = -ETIMEDOUT;
391 goto out;
392 }
393 }
394
395 irqstat = esdhc_read32(®s->irqstat);
396
397 if (irqstat & CMD_ERR) {
398 err = -ECOMM;
399 goto out;
400 }
401
402 if (irqstat & IRQSTAT_CTOE) {
403 err = -ETIMEDOUT;
404 goto out;
405 }
406
407 /* Workaround for ESDHC errata ENGcm03648 */
408 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
409 int timeout = 6000;
410
411 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
412 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
413 PRSSTAT_DAT0)) {
414 udelay(100);
415 timeout--;
416 }
417
418 if (timeout <= 0) {
419 printf("Timeout waiting for DAT0 to go high!\n");
420 err = -ETIMEDOUT;
421 goto out;
422 }
423 }
424
425 /* Copy the response to the response buffer */
426 if (cmd->resp_type & MMC_RSP_136) {
427 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
428
429 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
430 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
431 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
432 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
433 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
434 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
435 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
436 cmd->response[3] = (cmdrsp0 << 8);
437 } else
438 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
439
440 /* Wait until all of the blocks are transferred */
441 if (data) {
442 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
443 esdhc_pio_read_write(priv, data);
444 } else {
445 flags = DATA_COMPLETE;
446 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
447 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
448 flags = IRQSTAT_BRR;
449
450 do {
451 irqstat = esdhc_read32(®s->irqstat);
452
453 if (irqstat & IRQSTAT_DTOE) {
454 err = -ETIMEDOUT;
455 goto out;
456 }
457
458 if (irqstat & DATA_ERR) {
459 err = -ECOMM;
460 goto out;
461 }
462 } while ((irqstat & flags) != flags);
463
464 /*
465 * Need invalidate the dcache here again to avoid any
466 * cache-fill during the DMA operations such as the
467 * speculative pre-fetching etc.
468 */
469 dma_unmap_single(priv->dma_addr,
470 data->blocks * data->blocksize,
471 mmc_get_dma_dir(data));
472 }
473 }
474
475 out:
476 /* Reset CMD and DATA portions on error */
477 if (err) {
478 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
479 SYSCTL_RSTC);
480 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
481 ;
482
483 if (data) {
484 esdhc_write32(®s->sysctl,
485 esdhc_read32(®s->sysctl) |
486 SYSCTL_RSTD);
487 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
488 ;
489 }
490 }
491
492 esdhc_write32(®s->irqstat, -1);
493
494 return err;
495 }
496
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)497 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
498 {
499 struct fsl_esdhc *regs = priv->esdhc_regs;
500 int div = 1;
501 int pre_div = 2;
502 unsigned int sdhc_clk = priv->sdhc_clk;
503 u32 time_out;
504 u32 value;
505 uint clk;
506
507 if (clock < mmc->cfg->f_min)
508 clock = mmc->cfg->f_min;
509
510 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
511 pre_div *= 2;
512
513 while (sdhc_clk / (div * pre_div) > clock && div < 16)
514 div++;
515
516 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
517 clock == 200000000 && mmc->selected_mode == MMC_HS_400) {
518 u32 div_ratio = pre_div * div;
519
520 if (div_ratio <= 4) {
521 pre_div = 4;
522 div = 1;
523 } else if (div_ratio <= 8) {
524 pre_div = 4;
525 div = 2;
526 } else if (div_ratio <= 12) {
527 pre_div = 4;
528 div = 3;
529 } else {
530 printf("unsupported clock division.\n");
531 }
532 }
533
534 mmc->clock = sdhc_clk / pre_div / div;
535 priv->clock = mmc->clock;
536
537 pre_div >>= 1;
538 div -= 1;
539
540 clk = (pre_div << 8) | (div << 4);
541
542 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
543
544 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
545
546 time_out = 20;
547 value = PRSSTAT_SDSTB;
548 while (!(esdhc_read32(®s->prsstat) & value)) {
549 if (time_out == 0) {
550 printf("fsl_esdhc: Internal clock never stabilised.\n");
551 break;
552 }
553 time_out--;
554 mdelay(1);
555 }
556
557 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
558 }
559
esdhc_clock_control(struct fsl_esdhc_priv * priv,bool enable)560 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
561 {
562 struct fsl_esdhc *regs = priv->esdhc_regs;
563 u32 value;
564 u32 time_out;
565
566 value = esdhc_read32(®s->sysctl);
567
568 if (enable)
569 value |= SYSCTL_CKEN;
570 else
571 value &= ~SYSCTL_CKEN;
572
573 esdhc_write32(®s->sysctl, value);
574
575 time_out = 20;
576 value = PRSSTAT_SDSTB;
577 while (!(esdhc_read32(®s->prsstat) & value)) {
578 if (time_out == 0) {
579 printf("fsl_esdhc: Internal clock never stabilised.\n");
580 break;
581 }
582 time_out--;
583 mdelay(1);
584 }
585 }
586
esdhc_flush_async_fifo(struct fsl_esdhc_priv * priv)587 static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
588 {
589 struct fsl_esdhc *regs = priv->esdhc_regs;
590 u32 time_out;
591
592 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_FAF);
593
594 time_out = 20;
595 while (esdhc_read32(®s->esdhcctl) & ESDHCCTL_FAF) {
596 if (time_out == 0) {
597 printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
598 break;
599 }
600 time_out--;
601 mdelay(1);
602 }
603 }
604
esdhc_tuning_block_enable(struct fsl_esdhc_priv * priv,bool en)605 static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
606 bool en)
607 {
608 struct fsl_esdhc *regs = priv->esdhc_regs;
609
610 esdhc_clock_control(priv, false);
611 esdhc_flush_async_fifo(priv);
612 if (en)
613 esdhc_setbits32(®s->tbctl, TBCTL_TB_EN);
614 else
615 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
616 esdhc_clock_control(priv, true);
617 }
618
esdhc_exit_hs400(struct fsl_esdhc_priv * priv)619 static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
620 {
621 struct fsl_esdhc *regs = priv->esdhc_regs;
622
623 esdhc_clrbits32(®s->sdtimingctl, FLW_CTL_BG);
624 esdhc_clrbits32(®s->sdclkctl, CMD_CLK_CTL);
625
626 esdhc_clock_control(priv, false);
627 esdhc_clrbits32(®s->tbctl, HS400_MODE);
628 esdhc_clock_control(priv, true);
629
630 esdhc_clrbits32(®s->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
631 esdhc_clrbits32(®s->tbctl, HS400_WNDW_ADJUST);
632
633 esdhc_tuning_block_enable(priv, false);
634 }
635
esdhc_set_timing(struct fsl_esdhc_priv * priv,enum bus_mode mode)636 static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
637 {
638 struct fsl_esdhc *regs = priv->esdhc_regs;
639 ulong start;
640 u32 val;
641
642 /* Exit HS400 mode before setting any other mode */
643 if (esdhc_read32(®s->tbctl) & HS400_MODE &&
644 mode != MMC_HS_400)
645 esdhc_exit_hs400(priv);
646
647 esdhc_clock_control(priv, false);
648
649 if (mode == MMC_HS_200)
650 esdhc_clrsetbits32(®s->autoc12err, UHSM_MASK,
651 UHSM_SDR104_HS200);
652 if (mode == MMC_HS_400) {
653 esdhc_setbits32(®s->tbctl, HS400_MODE);
654 esdhc_setbits32(®s->sdclkctl, CMD_CLK_CTL);
655 esdhc_clock_control(priv, true);
656
657 if (priv->clock == 200000000)
658 esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL);
659
660 esdhc_setbits32(®s->dllcfg0, DLL_ENABLE);
661
662 esdhc_setbits32(®s->dllcfg0, DLL_RESET);
663 udelay(1);
664 esdhc_clrbits32(®s->dllcfg0, DLL_RESET);
665
666 start = get_timer(0);
667 val = DLL_STS_SLV_LOCK;
668 while (!(esdhc_read32(®s->dllstat0) & val)) {
669 if (get_timer(start) > 1000) {
670 printf("fsl_esdhc: delay chain lock timeout\n");
671 return -ETIMEDOUT;
672 }
673 }
674
675 esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST);
676
677 esdhc_clock_control(priv, false);
678 esdhc_flush_async_fifo(priv);
679 }
680 esdhc_clock_control(priv, true);
681 return 0;
682 }
683
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)684 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
685 {
686 struct fsl_esdhc *regs = priv->esdhc_regs;
687 int ret;
688
689 if (priv->is_sdhc_per_clk) {
690 /* Select to use peripheral clock */
691 esdhc_clock_control(priv, false);
692 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
693 esdhc_clock_control(priv, true);
694 }
695
696 if (mmc->selected_mode == MMC_HS_400)
697 esdhc_tuning_block_enable(priv, true);
698
699 /* Set the clock speed */
700 if (priv->clock != mmc->clock)
701 set_sysctl(priv, mmc, mmc->clock);
702
703 /* Set timing */
704 ret = esdhc_set_timing(priv, mmc->selected_mode);
705 if (ret)
706 return ret;
707
708 /* Set the bus width */
709 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
710
711 if (mmc->bus_width == 4)
712 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
713 else if (mmc->bus_width == 8)
714 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
715
716 return 0;
717 }
718
esdhc_enable_cache_snooping(struct fsl_esdhc * regs)719 static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
720 {
721 #ifdef CONFIG_ARCH_MPC830X
722 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
723 sysconf83xx_t *sysconf = &immr->sysconf;
724
725 setbits_be32(&sysconf->sdhccr, 0x02000000);
726 #else
727 esdhc_write32(®s->esdhcctl, 0x00000040);
728 #endif
729 }
730
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)731 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
732 {
733 struct fsl_esdhc *regs = priv->esdhc_regs;
734 ulong start;
735
736 /* Reset the entire host controller */
737 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
738
739 /* Wait until the controller is available */
740 start = get_timer(0);
741 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
742 if (get_timer(start) > 1000)
743 return -ETIMEDOUT;
744 }
745
746 /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
747 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
748
749 esdhc_enable_cache_snooping(regs);
750
751 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
752
753 /* Set the initial clock speed */
754 set_sysctl(priv, mmc, 400000);
755
756 /* Disable the BRR and BWR bits in IRQSTAT */
757 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
758
759 /* Put the PROCTL reg back to the default */
760 esdhc_write32(®s->proctl, PROCTL_INIT);
761
762 /* Set timout to the maximum value */
763 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
764
765 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
766 esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
767
768 return 0;
769 }
770
esdhc_getcd_common(struct fsl_esdhc_priv * priv)771 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
772 {
773 struct fsl_esdhc *regs = priv->esdhc_regs;
774
775 #ifdef CONFIG_ESDHC_DETECT_QUIRK
776 if (CONFIG_ESDHC_DETECT_QUIRK)
777 return 1;
778 #endif
779 if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
780 return 1;
781
782 return 0;
783 }
784
fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv * priv,struct mmc_config * cfg)785 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
786 struct mmc_config *cfg)
787 {
788 struct fsl_esdhc *regs = priv->esdhc_regs;
789 u32 caps;
790
791 caps = esdhc_read32(®s->hostcapblt);
792
793 /*
794 * For eSDHC, power supply is through peripheral circuit. Some eSDHC
795 * versions have value 0 of the bit but that does not reflect the
796 * truth. 3.3V is common for SD/MMC, and is supported for all boards
797 * with eSDHC in current u-boot. So, make 3.3V is supported in
798 * default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled
799 * if future board does not support 3.3V.
800 */
801 caps |= HOSTCAPBLT_VS33;
802 if (IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
803 caps &= ~HOSTCAPBLT_VS33;
804
805 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
806 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
807 if (caps & HOSTCAPBLT_VS18)
808 cfg->voltages |= MMC_VDD_165_195;
809 if (caps & HOSTCAPBLT_VS30)
810 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
811 if (caps & HOSTCAPBLT_VS33)
812 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
813
814 cfg->name = "FSL_SDHC";
815
816 if (caps & HOSTCAPBLT_HSS)
817 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
818
819 cfg->f_min = 400000;
820 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
821 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
822 }
823
824 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)825 __weak int esdhc_status_fixup(void *blob, const char *compat)
826 {
827 if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
828 do_fixup_by_compat(blob, compat, "status", "disabled",
829 sizeof("disabled"), 1);
830 return 1;
831 }
832
833 return 0;
834 }
835
836
837 #if CONFIG_IS_ENABLED(DM_MMC)
838 static int fsl_esdhc_get_cd(struct udevice *dev);
esdhc_disable_for_no_card(void * blob)839 static void esdhc_disable_for_no_card(void *blob)
840 {
841 struct udevice *dev;
842
843 for (uclass_first_device(UCLASS_MMC, &dev);
844 dev;
845 uclass_next_device(&dev)) {
846 char esdhc_path[50];
847
848 if (fsl_esdhc_get_cd(dev))
849 continue;
850
851 snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
852 (unsigned long)dev_read_addr(dev));
853 do_fixup_by_path(blob, esdhc_path, "status", "disabled",
854 sizeof("disabled"), 1);
855 }
856 }
857 #else
esdhc_disable_for_no_card(void * blob)858 static void esdhc_disable_for_no_card(void *blob)
859 {
860 }
861 #endif
862
fdt_fixup_esdhc(void * blob,struct bd_info * bd)863 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
864 {
865 const char *compat = "fsl,esdhc";
866
867 if (esdhc_status_fixup(blob, compat))
868 return;
869
870 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
871 esdhc_disable_for_no_card(blob);
872
873 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
874 gd->arch.sdhc_clk, 1);
875 }
876 #endif
877
878 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)879 static int esdhc_getcd(struct mmc *mmc)
880 {
881 struct fsl_esdhc_priv *priv = mmc->priv;
882
883 return esdhc_getcd_common(priv);
884 }
885
esdhc_init(struct mmc * mmc)886 static int esdhc_init(struct mmc *mmc)
887 {
888 struct fsl_esdhc_priv *priv = mmc->priv;
889
890 return esdhc_init_common(priv, mmc);
891 }
892
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)893 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
894 struct mmc_data *data)
895 {
896 struct fsl_esdhc_priv *priv = mmc->priv;
897
898 return esdhc_send_cmd_common(priv, mmc, cmd, data);
899 }
900
esdhc_set_ios(struct mmc * mmc)901 static int esdhc_set_ios(struct mmc *mmc)
902 {
903 struct fsl_esdhc_priv *priv = mmc->priv;
904
905 return esdhc_set_ios_common(priv, mmc);
906 }
907
908 static const struct mmc_ops esdhc_ops = {
909 .getcd = esdhc_getcd,
910 .init = esdhc_init,
911 .send_cmd = esdhc_send_cmd,
912 .set_ios = esdhc_set_ios,
913 };
914
fsl_esdhc_initialize(struct bd_info * bis,struct fsl_esdhc_cfg * cfg)915 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
916 {
917 struct fsl_esdhc_plat *plat;
918 struct fsl_esdhc_priv *priv;
919 struct mmc_config *mmc_cfg;
920 struct mmc *mmc;
921
922 if (!cfg)
923 return -EINVAL;
924
925 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
926 if (!priv)
927 return -ENOMEM;
928 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
929 if (!plat) {
930 free(priv);
931 return -ENOMEM;
932 }
933
934 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
935 priv->sdhc_clk = cfg->sdhc_clk;
936 if (gd->arch.sdhc_per_clk)
937 priv->is_sdhc_per_clk = true;
938
939 mmc_cfg = &plat->cfg;
940
941 if (cfg->max_bus_width == 8) {
942 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
943 MMC_MODE_8BIT;
944 } else if (cfg->max_bus_width == 4) {
945 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
946 } else if (cfg->max_bus_width == 1) {
947 mmc_cfg->host_caps |= MMC_MODE_1BIT;
948 } else {
949 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
950 MMC_MODE_8BIT;
951 printf("No max bus width provided. Assume 8-bit supported.\n");
952 }
953
954 if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
955 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
956
957 mmc_cfg->ops = &esdhc_ops;
958
959 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
960
961 mmc = mmc_create(mmc_cfg, priv);
962 if (!mmc)
963 return -EIO;
964
965 priv->mmc = mmc;
966 return 0;
967 }
968
fsl_esdhc_mmc_init(struct bd_info * bis)969 int fsl_esdhc_mmc_init(struct bd_info *bis)
970 {
971 struct fsl_esdhc_cfg *cfg;
972
973 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
974 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
975 /* Prefer peripheral clock which provides higher frequency. */
976 if (gd->arch.sdhc_per_clk)
977 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
978 else
979 cfg->sdhc_clk = gd->arch.sdhc_clk;
980 return fsl_esdhc_initialize(bis, cfg);
981 }
982 #else /* DM_MMC */
fsl_esdhc_probe(struct udevice * dev)983 static int fsl_esdhc_probe(struct udevice *dev)
984 {
985 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
986 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
987 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
988 u32 caps, hostver;
989 fdt_addr_t addr;
990 struct mmc *mmc;
991 int ret;
992
993 addr = dev_read_addr(dev);
994 if (addr == FDT_ADDR_T_NONE)
995 return -EINVAL;
996 #ifdef CONFIG_PPC
997 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
998 #else
999 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1000 #endif
1001 priv->dev = dev;
1002
1003 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
1004 /*
1005 * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
1006 * is set in the host capabilities register.
1007 */
1008 caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
1009 hostver = esdhc_read32(&priv->esdhc_regs->hostver);
1010 if (caps & HOSTCAPBLT_DMAS &&
1011 HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
1012 priv->adma_desc_table = sdhci_adma_init();
1013 if (!priv->adma_desc_table)
1014 debug("Could not allocate ADMA tables, falling back to SDMA\n");
1015 }
1016 }
1017
1018 if (gd->arch.sdhc_per_clk) {
1019 priv->sdhc_clk = gd->arch.sdhc_per_clk;
1020 priv->is_sdhc_per_clk = true;
1021 } else {
1022 priv->sdhc_clk = gd->arch.sdhc_clk;
1023 }
1024
1025 if (priv->sdhc_clk <= 0) {
1026 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1027 return -EINVAL;
1028 }
1029
1030 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
1031
1032 mmc_of_parse(dev, &plat->cfg);
1033
1034 mmc = &plat->mmc;
1035 mmc->cfg = &plat->cfg;
1036 mmc->dev = dev;
1037
1038 upriv->mmc = mmc;
1039
1040 ret = esdhc_init_common(priv, mmc);
1041 if (ret)
1042 return ret;
1043
1044 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
1045 !fsl_esdhc_get_cd(dev))
1046 esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
1047
1048 return 0;
1049 }
1050
fsl_esdhc_get_cd(struct udevice * dev)1051 static int fsl_esdhc_get_cd(struct udevice *dev)
1052 {
1053 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1054 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1055
1056 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
1057 return 1;
1058
1059 return esdhc_getcd_common(priv);
1060 }
1061
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1062 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1063 struct mmc_data *data)
1064 {
1065 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1066 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1067
1068 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1069 }
1070
fsl_esdhc_set_ios(struct udevice * dev)1071 static int fsl_esdhc_set_ios(struct udevice *dev)
1072 {
1073 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1074 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1075
1076 return esdhc_set_ios_common(priv, &plat->mmc);
1077 }
1078
fsl_esdhc_reinit(struct udevice * dev)1079 static int fsl_esdhc_reinit(struct udevice *dev)
1080 {
1081 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1082 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1083
1084 return esdhc_init_common(priv, &plat->mmc);
1085 }
1086
1087 #ifdef MMC_SUPPORTS_TUNING
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)1088 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
1089 {
1090 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1091 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1092 struct fsl_esdhc *regs = priv->esdhc_regs;
1093 struct mmc *mmc = &plat->mmc;
1094 u32 val, irqstaten;
1095 int i;
1096
1097 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
1098 plat->mmc.hs400_tuning)
1099 set_sysctl(priv, mmc, mmc->clock);
1100
1101 esdhc_tuning_block_enable(priv, true);
1102 esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING);
1103
1104 irqstaten = esdhc_read32(®s->irqstaten);
1105 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
1106
1107 for (i = 0; i < MAX_TUNING_LOOP; i++) {
1108 mmc_send_tuning(mmc, opcode, NULL);
1109 mdelay(1);
1110
1111 val = esdhc_read32(®s->autoc12err);
1112 if (!(val & EXECUTE_TUNING)) {
1113 if (val & SMPCLKSEL)
1114 break;
1115 }
1116 }
1117
1118 esdhc_write32(®s->irqstaten, irqstaten);
1119
1120 if (i != MAX_TUNING_LOOP) {
1121 if (plat->mmc.hs400_tuning)
1122 esdhc_setbits32(®s->sdtimingctl, FLW_CTL_BG);
1123 return 0;
1124 }
1125
1126 printf("fsl_esdhc: tuning failed!\n");
1127 esdhc_clrbits32(®s->autoc12err, SMPCLKSEL);
1128 esdhc_clrbits32(®s->autoc12err, EXECUTE_TUNING);
1129 esdhc_tuning_block_enable(priv, false);
1130 return -ETIMEDOUT;
1131 }
1132 #endif
1133
fsl_esdhc_hs400_prepare_ddr(struct udevice * dev)1134 int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
1135 {
1136 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1137
1138 esdhc_tuning_block_enable(priv, false);
1139 return 0;
1140 }
1141
fsl_esdhc_wait_dat0(struct udevice * dev,int state,int timeout_us)1142 static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1143 int timeout_us)
1144 {
1145 int ret;
1146 u32 tmp;
1147 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1148 struct fsl_esdhc *regs = priv->esdhc_regs;
1149
1150 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
1151 !!(tmp & PRSSTAT_DAT0) == !!state,
1152 timeout_us);
1153 return ret;
1154 }
1155
1156 static const struct dm_mmc_ops fsl_esdhc_ops = {
1157 .get_cd = fsl_esdhc_get_cd,
1158 .send_cmd = fsl_esdhc_send_cmd,
1159 .set_ios = fsl_esdhc_set_ios,
1160 #ifdef MMC_SUPPORTS_TUNING
1161 .execute_tuning = fsl_esdhc_execute_tuning,
1162 #endif
1163 .reinit = fsl_esdhc_reinit,
1164 .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
1165 .wait_dat0 = fsl_esdhc_wait_dat0,
1166 };
1167
1168 static const struct udevice_id fsl_esdhc_ids[] = {
1169 { .compatible = "fsl,esdhc", },
1170 { /* sentinel */ }
1171 };
1172
fsl_esdhc_bind(struct udevice * dev)1173 static int fsl_esdhc_bind(struct udevice *dev)
1174 {
1175 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1176
1177 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1178 }
1179
1180 U_BOOT_DRIVER(fsl_esdhc) = {
1181 .name = "fsl-esdhc-mmc",
1182 .id = UCLASS_MMC,
1183 .of_match = fsl_esdhc_ids,
1184 .ops = &fsl_esdhc_ops,
1185 .bind = fsl_esdhc_bind,
1186 .probe = fsl_esdhc_probe,
1187 .plat_auto = sizeof(struct fsl_esdhc_plat),
1188 .priv_auto = sizeof(struct fsl_esdhc_priv),
1189 };
1190 #endif
1191