1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell SD Host Controller Interface
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <malloc.h>
9 #include <sdhci.h>
10 #include <asm/global_data.h>
11 #include <linux/mbus.h>
12
13 #define MVSDH_NAME "mv_sdh"
14
15 #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
16 #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
17
sdhci_mvebu_mbus_config(void __iomem * base)18 static void sdhci_mvebu_mbus_config(void __iomem *base)
19 {
20 const struct mbus_dram_target_info *dram;
21 int i;
22
23 dram = mvebu_mbus_dram_info();
24
25 for (i = 0; i < 4; i++) {
26 writel(0, base + SDHCI_WINDOW_CTRL(i));
27 writel(0, base + SDHCI_WINDOW_BASE(i));
28 }
29
30 for (i = 0; i < dram->num_cs; i++) {
31 const struct mbus_dram_window *cs = dram->cs + i;
32
33 /* Write size, attributes and target id to control register */
34 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
35 (dram->mbus_dram_target_id << 4) | 1,
36 base + SDHCI_WINDOW_CTRL(i));
37
38 /* Write base address to base register */
39 writel(cs->base, base + SDHCI_WINDOW_BASE(i));
40 }
41 }
42
43 #ifndef CONFIG_DM_MMC
44
45 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
46 static struct sdhci_ops mv_ops;
47 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
48
mv_sdh_init(unsigned long regbase,u32 max_clk,u32 min_clk,u32 quirks)49 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
50 {
51 struct sdhci_host *host = NULL;
52 host = calloc(1, sizeof(*host));
53 if (!host) {
54 printf("sdh_host malloc fail!\n");
55 return -ENOMEM;
56 }
57
58 host->name = MVSDH_NAME;
59 host->ioaddr = (void *)regbase;
60 host->quirks = quirks;
61 host->max_clk = max_clk;
62 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
63 memset(&mv_ops, 0, sizeof(struct sdhci_ops));
64 host->ops = &mv_ops;
65 #endif
66
67 if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
68 /* Configure SDHCI MBUS mbus bridge windows */
69 sdhci_mvebu_mbus_config((void __iomem *)regbase);
70 }
71
72 return add_sdhci(host, 0, min_clk);
73 }
74
75 #else
76
77 DECLARE_GLOBAL_DATA_PTR;
78
79 struct mv_sdhci_plat {
80 struct mmc_config cfg;
81 struct mmc mmc;
82 };
83
mv_sdhci_probe(struct udevice * dev)84 static int mv_sdhci_probe(struct udevice *dev)
85 {
86 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
87 struct mv_sdhci_plat *plat = dev_get_plat(dev);
88 struct sdhci_host *host = dev_get_priv(dev);
89 int ret;
90
91 host->name = MVSDH_NAME;
92 host->ioaddr = dev_read_addr_ptr(dev);
93 host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
94 host->mmc = &plat->mmc;
95 host->mmc->dev = dev;
96 host->mmc->priv = host;
97
98 ret = mmc_of_parse(dev, &plat->cfg);
99 if (ret)
100 return ret;
101
102 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
103 if (ret)
104 return ret;
105
106 if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
107 /* Configure SDHCI MBUS mbus bridge windows */
108 sdhci_mvebu_mbus_config(host->ioaddr);
109 }
110
111 upriv->mmc = host->mmc;
112
113 return sdhci_probe(dev);
114 }
115
mv_sdhci_bind(struct udevice * dev)116 static int mv_sdhci_bind(struct udevice *dev)
117 {
118 struct mv_sdhci_plat *plat = dev_get_plat(dev);
119
120 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
121 }
122
123 static const struct udevice_id mv_sdhci_ids[] = {
124 { .compatible = "marvell,armada-380-sdhci" },
125 { }
126 };
127
128 U_BOOT_DRIVER(mv_sdhci_drv) = {
129 .name = MVSDH_NAME,
130 .id = UCLASS_MMC,
131 .of_match = mv_sdhci_ids,
132 .bind = mv_sdhci_bind,
133 .probe = mv_sdhci_probe,
134 .ops = &sdhci_ops,
135 .priv_auto = sizeof(struct sdhci_host),
136 .plat_auto = sizeof(struct mv_sdhci_plat),
137 };
138 #endif /* CONFIG_DM_MMC */
139