1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
6 *
7 * MMC driver for allwinner sunxi platform.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <mmc.h>
16 #include <clk.h>
17 #include <reset.h>
18 #include <asm/gpio.h>
19 #include <asm/io.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/mmc.h>
23 #include <linux/delay.h>
24
25 #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
26 #define CCM_MMC_CTRL_MODE_SEL_NEW 0
27 #endif
28
29 struct sunxi_mmc_plat {
30 struct mmc_config cfg;
31 struct mmc mmc;
32 };
33
34 struct sunxi_mmc_priv {
35 unsigned mmc_no;
36 uint32_t *mclkreg;
37 unsigned fatal_err;
38 struct gpio_desc cd_gpio; /* Change Detect GPIO */
39 struct sunxi_mmc *reg;
40 struct mmc_config cfg;
41 };
42
43 #if !CONFIG_IS_ENABLED(DM_MMC)
44 /* support 4 mmc hosts */
45 struct sunxi_mmc_priv mmc_host[4];
46
sunxi_mmc_getcd_gpio(int sdc_no)47 static int sunxi_mmc_getcd_gpio(int sdc_no)
48 {
49 switch (sdc_no) {
50 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
51 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
52 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
53 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
54 }
55 return -EINVAL;
56 }
57
mmc_resource_init(int sdc_no)58 static int mmc_resource_init(int sdc_no)
59 {
60 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
61 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
62 int cd_pin, ret = 0;
63
64 debug("init mmc %d resource\n", sdc_no);
65
66 switch (sdc_no) {
67 case 0:
68 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
69 priv->mclkreg = &ccm->sd0_clk_cfg;
70 break;
71 case 1:
72 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
73 priv->mclkreg = &ccm->sd1_clk_cfg;
74 break;
75 #ifdef SUNXI_MMC2_BASE
76 case 2:
77 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
78 priv->mclkreg = &ccm->sd2_clk_cfg;
79 break;
80 #endif
81 #ifdef SUNXI_MMC3_BASE
82 case 3:
83 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
84 priv->mclkreg = &ccm->sd3_clk_cfg;
85 break;
86 #endif
87 default:
88 printf("Wrong mmc number %d\n", sdc_no);
89 return -1;
90 }
91 priv->mmc_no = sdc_no;
92
93 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
94 if (cd_pin >= 0) {
95 ret = gpio_request(cd_pin, "mmc_cd");
96 if (!ret) {
97 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
98 ret = gpio_direction_input(cd_pin);
99 }
100 }
101
102 return ret;
103 }
104 #endif
105
106 /*
107 * All A64 and later MMC controllers feature auto-calibration. This would
108 * normally be detected via the compatible string, but we need something
109 * which works in the SPL as well.
110 */
sunxi_mmc_can_calibrate(void)111 static bool sunxi_mmc_can_calibrate(void)
112 {
113 return IS_ENABLED(CONFIG_MACH_SUN50I) ||
114 IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
115 IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
116 IS_ENABLED(CONFIG_MACH_SUN8I_R40);
117 }
118
mmc_set_mod_clk(struct sunxi_mmc_priv * priv,unsigned int hz)119 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
120 {
121 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
122 bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
123 u32 val = 0;
124
125 /* A83T support new mode only on eMMC */
126 if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
127 new_mode = false;
128
129 if (hz <= 24000000) {
130 pll = CCM_MMC_CTRL_OSCM24;
131 pll_hz = 24000000;
132 } else {
133 #ifdef CONFIG_MACH_SUN9I
134 pll = CCM_MMC_CTRL_PLL_PERIPH0;
135 pll_hz = clock_get_pll4_periph0();
136 #else
137 /*
138 * SoCs since the A64 (H5, H6, H616) actually use the doubled
139 * rate of PLL6/PERIPH0 as an input clock, but compensate for
140 * that with a fixed post-divider of 2 in the mod clock.
141 * This cancels each other out, so for simplicity we just
142 * pretend it's always PLL6 without a post divider here.
143 */
144 pll = CCM_MMC_CTRL_PLL6;
145 pll_hz = clock_get_pll6();
146 #endif
147 }
148
149 div = pll_hz / hz;
150 if (pll_hz % hz)
151 div++;
152
153 n = 0;
154 while (div > 16) {
155 n++;
156 div = (div + 1) / 2;
157 }
158
159 if (n > 3) {
160 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
161 hz);
162 return -1;
163 }
164
165 /* determine delays */
166 if (hz <= 400000) {
167 oclk_dly = 0;
168 sclk_dly = 0;
169 } else if (hz <= 25000000) {
170 oclk_dly = 0;
171 sclk_dly = 5;
172 } else {
173 if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
174 if (hz <= 52000000)
175 oclk_dly = 5;
176 else
177 oclk_dly = 2;
178 } else {
179 if (hz <= 52000000)
180 oclk_dly = 3;
181 else
182 oclk_dly = 1;
183 }
184 sclk_dly = 4;
185 }
186
187 if (new_mode) {
188 val |= CCM_MMC_CTRL_MODE_SEL_NEW;
189 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
190 }
191
192 if (!sunxi_mmc_can_calibrate()) {
193 /*
194 * Use hardcoded delay values if controller doesn't support
195 * calibration
196 */
197 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
198 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
199 }
200
201 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
202 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
203
204 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
205 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
206
207 return 0;
208 }
209
mmc_update_clk(struct sunxi_mmc_priv * priv)210 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
211 {
212 unsigned int cmd;
213 unsigned timeout_msecs = 2000;
214 unsigned long start = get_timer(0);
215
216 cmd = SUNXI_MMC_CMD_START |
217 SUNXI_MMC_CMD_UPCLK_ONLY |
218 SUNXI_MMC_CMD_WAIT_PRE_OVER;
219
220 writel(cmd, &priv->reg->cmd);
221 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
222 if (get_timer(start) > timeout_msecs)
223 return -1;
224 }
225
226 /* clock update sets various irq status bits, clear these */
227 writel(readl(&priv->reg->rint), &priv->reg->rint);
228
229 return 0;
230 }
231
mmc_config_clock(struct sunxi_mmc_priv * priv,struct mmc * mmc)232 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
233 {
234 unsigned rval = readl(&priv->reg->clkcr);
235
236 /* Disable Clock */
237 rval &= ~SUNXI_MMC_CLK_ENABLE;
238 writel(rval, &priv->reg->clkcr);
239 if (mmc_update_clk(priv))
240 return -1;
241
242 /* Set mod_clk to new rate */
243 if (mmc_set_mod_clk(priv, mmc->clock))
244 return -1;
245
246 /* Clear internal divider */
247 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
248 writel(rval, &priv->reg->clkcr);
249
250 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
251 /* A64 supports calibration of delays on MMC controller and we
252 * have to set delay of zero before starting calibration.
253 * Allwinner BSP driver sets a delay only in the case of
254 * using HS400 which is not supported by mainline U-Boot or
255 * Linux at the moment
256 */
257 if (sunxi_mmc_can_calibrate())
258 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
259 #endif
260
261 /* Re-enable Clock */
262 rval |= SUNXI_MMC_CLK_ENABLE;
263 writel(rval, &priv->reg->clkcr);
264 if (mmc_update_clk(priv))
265 return -1;
266
267 return 0;
268 }
269
sunxi_mmc_set_ios_common(struct sunxi_mmc_priv * priv,struct mmc * mmc)270 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
271 struct mmc *mmc)
272 {
273 debug("set ios: bus_width: %x, clock: %d\n",
274 mmc->bus_width, mmc->clock);
275
276 /* Change clock first */
277 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
278 priv->fatal_err = 1;
279 return -EINVAL;
280 }
281
282 /* Change bus width */
283 if (mmc->bus_width == 8)
284 writel(0x2, &priv->reg->width);
285 else if (mmc->bus_width == 4)
286 writel(0x1, &priv->reg->width);
287 else
288 writel(0x0, &priv->reg->width);
289
290 return 0;
291 }
292
293 #if !CONFIG_IS_ENABLED(DM_MMC)
sunxi_mmc_core_init(struct mmc * mmc)294 static int sunxi_mmc_core_init(struct mmc *mmc)
295 {
296 struct sunxi_mmc_priv *priv = mmc->priv;
297
298 /* Reset controller */
299 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
300 udelay(1000);
301
302 return 0;
303 }
304 #endif
305
mmc_trans_data_by_cpu(struct sunxi_mmc_priv * priv,struct mmc * mmc,struct mmc_data * data)306 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
307 struct mmc_data *data)
308 {
309 const int reading = !!(data->flags & MMC_DATA_READ);
310 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
311 SUNXI_MMC_STATUS_FIFO_FULL;
312 unsigned i;
313 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
314 unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
315 unsigned timeout_msecs = word_cnt >> 6;
316 uint32_t status;
317 unsigned long start;
318
319 if (timeout_msecs < 2000)
320 timeout_msecs = 2000;
321
322 /* Always read / write data through the CPU */
323 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
324
325 start = get_timer(0);
326
327 for (i = 0; i < word_cnt;) {
328 unsigned int in_fifo;
329
330 while ((status = readl(&priv->reg->status)) & status_bit) {
331 if (get_timer(start) > timeout_msecs)
332 return -1;
333 }
334
335 /*
336 * For writing we do not easily know the FIFO size, so have
337 * to check the FIFO status after every word written.
338 * TODO: For optimisation we could work out a minimum FIFO
339 * size across all SoCs, and use that together with the current
340 * fill level to write chunks of words.
341 */
342 if (!reading) {
343 writel(buff[i++], &priv->reg->fifo);
344 continue;
345 }
346
347 /*
348 * The status register holds the current FIFO level, so we
349 * can be sure to collect as many words from the FIFO
350 * register without checking the status register after every
351 * read. That saves half of the costly MMIO reads, effectively
352 * doubling the read performance.
353 * Some SoCs (A20) report a level of 0 if the FIFO is
354 * completely full (value masked out?). Use a safe minimal
355 * FIFO size in this case.
356 */
357 in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
358 if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
359 in_fifo = 32;
360 for (; in_fifo > 0; in_fifo--)
361 buff[i++] = readl_relaxed(&priv->reg->fifo);
362 dmb();
363 }
364
365 return 0;
366 }
367
mmc_rint_wait(struct sunxi_mmc_priv * priv,struct mmc * mmc,uint timeout_msecs,uint done_bit,const char * what)368 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
369 uint timeout_msecs, uint done_bit, const char *what)
370 {
371 unsigned int status;
372 unsigned long start = get_timer(0);
373
374 do {
375 status = readl(&priv->reg->rint);
376 if ((get_timer(start) > timeout_msecs) ||
377 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
378 debug("%s timeout %x\n", what,
379 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
380 return -ETIMEDOUT;
381 }
382 } while (!(status & done_bit));
383
384 return 0;
385 }
386
sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)387 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
388 struct mmc *mmc, struct mmc_cmd *cmd,
389 struct mmc_data *data)
390 {
391 unsigned int cmdval = SUNXI_MMC_CMD_START;
392 unsigned int timeout_msecs;
393 int error = 0;
394 unsigned int status = 0;
395 unsigned int bytecnt = 0;
396
397 if (priv->fatal_err)
398 return -1;
399 if (cmd->resp_type & MMC_RSP_BUSY)
400 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
401 if (cmd->cmdidx == 12)
402 return 0;
403
404 if (!cmd->cmdidx)
405 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
406 if (cmd->resp_type & MMC_RSP_PRESENT)
407 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
408 if (cmd->resp_type & MMC_RSP_136)
409 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
410 if (cmd->resp_type & MMC_RSP_CRC)
411 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
412
413 if (data) {
414 if ((u32)(long)data->dest & 0x3) {
415 error = -1;
416 goto out;
417 }
418
419 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
420 if (data->flags & MMC_DATA_WRITE)
421 cmdval |= SUNXI_MMC_CMD_WRITE;
422 if (data->blocks > 1)
423 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
424 writel(data->blocksize, &priv->reg->blksz);
425 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
426 }
427
428 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
429 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
430 writel(cmd->cmdarg, &priv->reg->arg);
431
432 if (!data)
433 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
434
435 /*
436 * transfer data and check status
437 * STATREG[2] : FIFO empty
438 * STATREG[3] : FIFO full
439 */
440 if (data) {
441 int ret = 0;
442
443 bytecnt = data->blocksize * data->blocks;
444 debug("trans data %d bytes\n", bytecnt);
445 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
446 ret = mmc_trans_data_by_cpu(priv, mmc, data);
447 if (ret) {
448 error = readl(&priv->reg->rint) &
449 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
450 error = -ETIMEDOUT;
451 goto out;
452 }
453 }
454
455 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
456 "cmd");
457 if (error)
458 goto out;
459
460 if (data) {
461 timeout_msecs = 120;
462 debug("cacl timeout %x msec\n", timeout_msecs);
463 error = mmc_rint_wait(priv, mmc, timeout_msecs,
464 data->blocks > 1 ?
465 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
466 SUNXI_MMC_RINT_DATA_OVER,
467 "data");
468 if (error)
469 goto out;
470 }
471
472 if (cmd->resp_type & MMC_RSP_BUSY) {
473 unsigned long start = get_timer(0);
474 timeout_msecs = 2000;
475
476 do {
477 status = readl(&priv->reg->status);
478 if (get_timer(start) > timeout_msecs) {
479 debug("busy timeout\n");
480 error = -ETIMEDOUT;
481 goto out;
482 }
483 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
484 }
485
486 if (cmd->resp_type & MMC_RSP_136) {
487 cmd->response[0] = readl(&priv->reg->resp3);
488 cmd->response[1] = readl(&priv->reg->resp2);
489 cmd->response[2] = readl(&priv->reg->resp1);
490 cmd->response[3] = readl(&priv->reg->resp0);
491 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
492 cmd->response[3], cmd->response[2],
493 cmd->response[1], cmd->response[0]);
494 } else {
495 cmd->response[0] = readl(&priv->reg->resp0);
496 debug("mmc resp 0x%08x\n", cmd->response[0]);
497 }
498 out:
499 if (error < 0) {
500 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
501 mmc_update_clk(priv);
502 }
503 writel(0xffffffff, &priv->reg->rint);
504 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
505 &priv->reg->gctrl);
506
507 return error;
508 }
509
510 #if !CONFIG_IS_ENABLED(DM_MMC)
sunxi_mmc_set_ios_legacy(struct mmc * mmc)511 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
512 {
513 struct sunxi_mmc_priv *priv = mmc->priv;
514
515 return sunxi_mmc_set_ios_common(priv, mmc);
516 }
517
sunxi_mmc_send_cmd_legacy(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)518 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
519 struct mmc_data *data)
520 {
521 struct sunxi_mmc_priv *priv = mmc->priv;
522
523 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
524 }
525
sunxi_mmc_getcd_legacy(struct mmc * mmc)526 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
527 {
528 struct sunxi_mmc_priv *priv = mmc->priv;
529 int cd_pin;
530
531 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
532 if (cd_pin < 0)
533 return 1;
534
535 return !gpio_get_value(cd_pin);
536 }
537
538 static const struct mmc_ops sunxi_mmc_ops = {
539 .send_cmd = sunxi_mmc_send_cmd_legacy,
540 .set_ios = sunxi_mmc_set_ios_legacy,
541 .init = sunxi_mmc_core_init,
542 .getcd = sunxi_mmc_getcd_legacy,
543 };
544
sunxi_mmc_init(int sdc_no)545 struct mmc *sunxi_mmc_init(int sdc_no)
546 {
547 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
548 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
549 struct mmc_config *cfg = &priv->cfg;
550 int ret;
551
552 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
553
554 cfg->name = "SUNXI SD/MMC";
555 cfg->ops = &sunxi_mmc_ops;
556
557 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
558 cfg->host_caps = MMC_MODE_4BIT;
559
560 if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
561 IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
562 cfg->host_caps = MMC_MODE_8BIT;
563
564 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
565 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
566
567 cfg->f_min = 400000;
568 cfg->f_max = 52000000;
569
570 if (mmc_resource_init(sdc_no) != 0)
571 return NULL;
572
573 /* config ahb clock */
574 debug("init mmc %d clock and io\n", sdc_no);
575 #if !defined(CONFIG_SUN50I_GEN_H6)
576 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
577
578 #ifdef CONFIG_SUNXI_GEN_SUN6I
579 /* unassert reset */
580 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
581 #endif
582 #if defined(CONFIG_MACH_SUN9I)
583 /* sun9i has a mmc-common module, also set the gate and reset there */
584 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
585 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
586 #endif
587 #else /* CONFIG_SUN50I_GEN_H6 */
588 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
589 /* unassert reset */
590 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
591 #endif
592 ret = mmc_set_mod_clk(priv, 24000000);
593 if (ret)
594 return NULL;
595
596 return mmc_create(cfg, priv);
597 }
598 #else
599
sunxi_mmc_set_ios(struct udevice * dev)600 static int sunxi_mmc_set_ios(struct udevice *dev)
601 {
602 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
603 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
604
605 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
606 }
607
sunxi_mmc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)608 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
609 struct mmc_data *data)
610 {
611 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
612 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
613
614 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
615 }
616
sunxi_mmc_getcd(struct udevice * dev)617 static int sunxi_mmc_getcd(struct udevice *dev)
618 {
619 struct mmc *mmc = mmc_get_mmc_dev(dev);
620 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
621
622 /* If polling, assume that the card is always present. */
623 if ((mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE) ||
624 (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL))
625 return 1;
626
627 if (dm_gpio_is_valid(&priv->cd_gpio)) {
628 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
629
630 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
631 return !cd_state;
632 else
633 return cd_state;
634 }
635 return 1;
636 }
637
638 static const struct dm_mmc_ops sunxi_mmc_ops = {
639 .send_cmd = sunxi_mmc_send_cmd,
640 .set_ios = sunxi_mmc_set_ios,
641 .get_cd = sunxi_mmc_getcd,
642 };
643
get_mclk_offset(void)644 static unsigned get_mclk_offset(void)
645 {
646 if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
647 return 0x410;
648
649 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
650 return 0x830;
651
652 return 0x88;
653 };
654
sunxi_mmc_probe(struct udevice * dev)655 static int sunxi_mmc_probe(struct udevice *dev)
656 {
657 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
658 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
659 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
660 struct reset_ctl_bulk reset_bulk;
661 struct clk gate_clk;
662 struct mmc_config *cfg = &plat->cfg;
663 struct ofnode_phandle_args args;
664 u32 *ccu_reg;
665 int ret;
666
667 cfg->name = dev->name;
668
669 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
670 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
671 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
672
673 cfg->f_min = 400000;
674 cfg->f_max = 52000000;
675
676 ret = mmc_of_parse(dev, cfg);
677 if (ret)
678 return ret;
679
680 priv->reg = dev_read_addr_ptr(dev);
681
682 /* We don't have a sunxi clock driver so find the clock address here */
683 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
684 1, &args);
685 if (ret)
686 return ret;
687 ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
688
689 priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
690 priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
691
692 ret = clk_get_by_name(dev, "ahb", &gate_clk);
693 if (!ret)
694 clk_enable(&gate_clk);
695
696 ret = reset_get_bulk(dev, &reset_bulk);
697 if (!ret)
698 reset_deassert_bulk(&reset_bulk);
699
700 ret = mmc_set_mod_clk(priv, 24000000);
701 if (ret)
702 return ret;
703
704 /* This GPIO is optional */
705 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
706 GPIOD_IS_IN)) {
707 int cd_pin = gpio_get_number(&priv->cd_gpio);
708
709 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
710 }
711
712 upriv->mmc = &plat->mmc;
713
714 /* Reset controller */
715 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
716 udelay(1000);
717
718 return 0;
719 }
720
sunxi_mmc_bind(struct udevice * dev)721 static int sunxi_mmc_bind(struct udevice *dev)
722 {
723 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
724
725 return mmc_bind(dev, &plat->mmc, &plat->cfg);
726 }
727
728 static const struct udevice_id sunxi_mmc_ids[] = {
729 { .compatible = "allwinner,sun4i-a10-mmc" },
730 { .compatible = "allwinner,sun5i-a13-mmc" },
731 { .compatible = "allwinner,sun7i-a20-mmc" },
732 { .compatible = "allwinner,sun8i-a83t-emmc" },
733 { .compatible = "allwinner,sun9i-a80-mmc" },
734 { .compatible = "allwinner,sun50i-a64-mmc" },
735 { .compatible = "allwinner,sun50i-a64-emmc" },
736 { .compatible = "allwinner,sun50i-h6-mmc" },
737 { .compatible = "allwinner,sun50i-h6-emmc" },
738 { .compatible = "allwinner,sun50i-a100-mmc" },
739 { .compatible = "allwinner,sun50i-a100-emmc" },
740 { /* sentinel */ }
741 };
742
743 U_BOOT_DRIVER(sunxi_mmc_drv) = {
744 .name = "sunxi_mmc",
745 .id = UCLASS_MMC,
746 .of_match = sunxi_mmc_ids,
747 .bind = sunxi_mmc_bind,
748 .probe = sunxi_mmc_probe,
749 .ops = &sunxi_mmc_ops,
750 .plat_auto = sizeof(struct sunxi_mmc_plat),
751 .priv_auto = sizeof(struct sunxi_mmc_priv),
752 };
753 #endif
754