1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NAND driver for TI DaVinci based boards.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
8 */
9
10 /*
11 *
12 * linux/drivers/mtd/nand/raw/nand_davinci.c
13 *
14 * NAND Flash Driver
15 *
16 * Copyright (C) 2006 Texas Instruments.
17 *
18 * ----------------------------------------------------------------------------
19 *
20 * ----------------------------------------------------------------------------
21 *
22 * Overview:
23 * This is a device driver for the NAND flash device found on the
24 * DaVinci board which utilizes the Samsung k9k2g08 part.
25 *
26 Modifications:
27 ver. 1.0: Feb 2005, Vinod/Sudhakar
28 -
29 */
30
31 #include <common.h>
32 #include <log.h>
33 #include <linux/mtd/rawnand.h>
34 #include <asm/io.h>
35 #include <nand.h>
36 #include <dm/uclass.h>
37 #include <asm/ti-common/davinci_nand.h>
38
39 /* Definitions for 4-bit hardware ECC */
40 #define NAND_TIMEOUT 10240
41 #define NAND_ECC_BUSY 0xC
42 #define NAND_4BITECC_MASK 0x03FF03FF
43 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
44 #define ECC_STATE_NO_ERR 0x0
45 #define ECC_STATE_TOO_MANY_ERRS 0x1
46 #define ECC_STATE_ERR_CORR_COMP_P 0x2
47 #define ECC_STATE_ERR_CORR_COMP_N 0x3
48
49 /*
50 * Exploit the little endianness of the ARM to do multi-byte transfers
51 * per device read. This can perform over twice as quickly as individual
52 * byte transfers when buffer alignment is conducive.
53 *
54 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
55 * the address bus. On Davinci EVM platforms this has always been true.
56 */
nand_davinci_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)57 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
58 {
59 struct nand_chip *chip = mtd_to_nand(mtd);
60 const u32 *nand = chip->IO_ADDR_R;
61
62 /* Make sure that buf is 32 bit aligned */
63 if (((int)buf & 0x3) != 0) {
64 if (((int)buf & 0x1) != 0) {
65 if (len) {
66 *buf = readb(nand);
67 buf += 1;
68 len--;
69 }
70 }
71
72 if (((int)buf & 0x3) != 0) {
73 if (len >= 2) {
74 *(u16 *)buf = readw(nand);
75 buf += 2;
76 len -= 2;
77 }
78 }
79 }
80
81 /* copy aligned data */
82 while (len >= 4) {
83 *(u32 *)buf = __raw_readl(nand);
84 buf += 4;
85 len -= 4;
86 }
87
88 /* mop up any remaining bytes */
89 if (len) {
90 if (len >= 2) {
91 *(u16 *)buf = readw(nand);
92 buf += 2;
93 len -= 2;
94 }
95
96 if (len)
97 *buf = readb(nand);
98 }
99 }
100
nand_davinci_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)101 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
102 int len)
103 {
104 struct nand_chip *chip = mtd_to_nand(mtd);
105 const u32 *nand = chip->IO_ADDR_W;
106
107 /* Make sure that buf is 32 bit aligned */
108 if (((int)buf & 0x3) != 0) {
109 if (((int)buf & 0x1) != 0) {
110 if (len) {
111 writeb(*buf, nand);
112 buf += 1;
113 len--;
114 }
115 }
116
117 if (((int)buf & 0x3) != 0) {
118 if (len >= 2) {
119 writew(*(u16 *)buf, nand);
120 buf += 2;
121 len -= 2;
122 }
123 }
124 }
125
126 /* copy aligned data */
127 while (len >= 4) {
128 __raw_writel(*(u32 *)buf, nand);
129 buf += 4;
130 len -= 4;
131 }
132
133 /* mop up any remaining bytes */
134 if (len) {
135 if (len >= 2) {
136 writew(*(u16 *)buf, nand);
137 buf += 2;
138 len -= 2;
139 }
140
141 if (len)
142 writeb(*buf, nand);
143 }
144 }
145
nand_davinci_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)146 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
147 unsigned int ctrl)
148 {
149 struct nand_chip *this = mtd_to_nand(mtd);
150 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
151
152 if (ctrl & NAND_CTRL_CHANGE) {
153 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
154
155 if (ctrl & NAND_CLE)
156 IO_ADDR_W |= MASK_CLE;
157 if (ctrl & NAND_ALE)
158 IO_ADDR_W |= MASK_ALE;
159 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
160 }
161
162 if (cmd != NAND_CMD_NONE)
163 writeb(cmd, IO_ADDR_W);
164 }
165
166 #ifdef CONFIG_SYS_NAND_HW_ECC
167
nand_davinci_readecc(struct mtd_info * mtd)168 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
169 {
170 u_int32_t ecc = 0;
171
172 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
173 CONFIG_SYS_NAND_CS - 2]));
174
175 return ecc;
176 }
177
nand_davinci_enable_hwecc(struct mtd_info * mtd,int mode)178 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
179 {
180 u_int32_t val;
181
182 /* reading the ECC result register resets the ECC calculation */
183 nand_davinci_readecc(mtd);
184
185 val = __raw_readl(&davinci_emif_regs->nandfcr);
186 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
187 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
188 __raw_writel(val, &davinci_emif_regs->nandfcr);
189 }
190
nand_davinci_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)191 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
192 u_char *ecc_code)
193 {
194 u_int32_t tmp;
195
196 tmp = nand_davinci_readecc(mtd);
197
198 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
199 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
200 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
201
202 /* Invert so that erased block ECC is correct */
203 tmp = ~tmp;
204
205 *ecc_code++ = tmp;
206 *ecc_code++ = tmp >> 8;
207 *ecc_code++ = tmp >> 16;
208
209 /* NOTE: the above code matches mainline Linux:
210 * .PQR.stu ==> ~PQRstu
211 *
212 * MontaVista/TI kernels encode those bytes differently, use
213 * complicated (and allegedly sometimes-wrong) correction code,
214 * and usually shipped with U-Boot that uses software ECC:
215 * .PQR.stu ==> PsQRtu
216 *
217 * If you need MV/TI compatible NAND I/O in U-Boot, it should
218 * be possible to (a) change the mangling above, (b) reverse
219 * that mangling in nand_davinci_correct_data() below.
220 */
221
222 return 0;
223 }
224
nand_davinci_correct_data(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)225 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
226 u_char *read_ecc, u_char *calc_ecc)
227 {
228 struct nand_chip *this = mtd_to_nand(mtd);
229 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
230 (read_ecc[2] << 16);
231 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
232 (calc_ecc[2] << 16);
233 u_int32_t diff = ecc_calc ^ ecc_nand;
234
235 if (diff) {
236 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
237 /* Correctable error */
238 if ((diff >> (12 + 3)) < this->ecc.size) {
239 uint8_t find_bit = 1 << ((diff >> 12) & 7);
240 uint32_t find_byte = diff >> (12 + 3);
241
242 dat[find_byte] ^= find_bit;
243 pr_debug("Correcting single "
244 "bit ECC error at offset: %d, bit: "
245 "%d\n", find_byte, find_bit);
246 return 1;
247 } else {
248 return -EBADMSG;
249 }
250 } else if (!(diff & (diff - 1))) {
251 /* Single bit ECC error in the ECC itself,
252 nothing to fix */
253 pr_debug("Single bit ECC error in " "ECC.\n");
254 return 1;
255 } else {
256 /* Uncorrectable error */
257 pr_debug("ECC UNCORRECTED_ERROR 1\n");
258 return -EBADMSG;
259 }
260 }
261 return 0;
262 }
263 #endif /* CONFIG_SYS_NAND_HW_ECC */
264
265 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
266 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
267 #if defined(CONFIG_SYS_NAND_PAGE_2K)
268 .eccbytes = 40,
269 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
270 .eccpos = {
271 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
272 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
273 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
274 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
275 },
276 .oobfree = {
277 {2, 4}, {16, 6}, {32, 6}, {48, 6},
278 },
279 #else
280 .eccpos = {
281 24, 25, 26, 27, 28,
282 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
283 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
284 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
285 59, 60, 61, 62, 63,
286 },
287 .oobfree = {
288 {.offset = 2, .length = 22, },
289 },
290 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
291 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
292 .eccbytes = 80,
293 .eccpos = {
294 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
295 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
296 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
297 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
298 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
299 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
300 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
301 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
302 },
303 .oobfree = {
304 {.offset = 2, .length = 46, },
305 },
306 #endif
307 };
308
309 #if defined CONFIG_KEYSTONE_RBL_NAND
310 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
311 #if defined(CONFIG_SYS_NAND_PAGE_2K)
312 .eccbytes = 40,
313 .eccpos = {
314 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
315 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
316 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
317 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
318 },
319 .oobfree = {
320 {.offset = 2, .length = 4, },
321 {.offset = 16, .length = 6, },
322 {.offset = 32, .length = 6, },
323 {.offset = 48, .length = 6, },
324 },
325 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
326 .eccbytes = 80,
327 .eccpos = {
328 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
329 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
330 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
331 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
332 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
333 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
334 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
335 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
336 },
337 .oobfree = {
338 {.offset = 2, .length = 4, },
339 {.offset = 16, .length = 6, },
340 {.offset = 32, .length = 6, },
341 {.offset = 48, .length = 6, },
342 {.offset = 64, .length = 6, },
343 {.offset = 80, .length = 6, },
344 {.offset = 96, .length = 6, },
345 {.offset = 112, .length = 6, },
346 },
347 #endif
348 };
349
350 #ifdef CONFIG_SYS_NAND_PAGE_2K
351 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11)
352 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
353 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12)
354 #endif
355
356 /**
357 * nand_davinci_write_page - write one page
358 * @mtd: MTD device structure
359 * @chip: NAND chip descriptor
360 * @buf: the data to write
361 * @oob_required: must write chip->oob_poi to OOB
362 * @page: page number to write
363 * @raw: use _raw version of write_page
364 */
nand_davinci_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)365 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
366 uint32_t offset, int data_len,
367 const uint8_t *buf, int oob_required,
368 int page, int raw)
369 {
370 int status;
371 int ret = 0;
372 struct nand_ecclayout *saved_ecc_layout;
373
374 /* save current ECC layout and assign Keystone RBL ECC layout */
375 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
376 saved_ecc_layout = chip->ecc.layout;
377 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
378 mtd->oobavail = chip->ecc.layout->oobavail;
379 }
380
381 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
382
383 if (unlikely(raw)) {
384 status = chip->ecc.write_page_raw(mtd, chip, buf,
385 oob_required, page);
386 } else {
387 status = chip->ecc.write_page(mtd, chip, buf,
388 oob_required, page);
389 }
390
391 if (status < 0) {
392 ret = status;
393 goto err;
394 }
395
396 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
397 status = chip->waitfunc(mtd, chip);
398
399 if (status & NAND_STATUS_FAIL) {
400 ret = -EIO;
401 goto err;
402 }
403
404 err:
405 /* restore ECC layout */
406 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
407 chip->ecc.layout = saved_ecc_layout;
408 mtd->oobavail = saved_ecc_layout->oobavail;
409 }
410
411 return ret;
412 }
413
414 /**
415 * nand_davinci_read_page_hwecc - hardware ECC based page read function
416 * @mtd: mtd info structure
417 * @chip: nand chip info structure
418 * @buf: buffer to store read data
419 * @oob_required: caller requires OOB data read to chip->oob_poi
420 * @page: page number to read
421 *
422 * Not for syndrome calculating ECC controllers which need a special oob layout.
423 */
nand_davinci_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)424 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
425 uint8_t *buf, int oob_required, int page)
426 {
427 int i, eccsize = chip->ecc.size;
428 int eccbytes = chip->ecc.bytes;
429 int eccsteps = chip->ecc.steps;
430 uint32_t *eccpos;
431 uint8_t *p = buf;
432 uint8_t *ecc_code = chip->buffers->ecccode;
433 uint8_t *ecc_calc = chip->buffers->ecccalc;
434 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
435
436 /* save current ECC layout and assign Keystone RBL ECC layout */
437 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
438 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
439 mtd->oobavail = chip->ecc.layout->oobavail;
440 }
441
442 eccpos = chip->ecc.layout->eccpos;
443
444 /* Read the OOB area first */
445 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
446 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
447 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
448
449 for (i = 0; i < chip->ecc.total; i++)
450 ecc_code[i] = chip->oob_poi[eccpos[i]];
451
452 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
453 int stat;
454
455 chip->ecc.hwctl(mtd, NAND_ECC_READ);
456 chip->read_buf(mtd, p, eccsize);
457 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
458
459 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
460 if (stat < 0)
461 mtd->ecc_stats.failed++;
462 else
463 mtd->ecc_stats.corrected += stat;
464 }
465
466 /* restore ECC layout */
467 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
468 chip->ecc.layout = saved_ecc_layout;
469 mtd->oobavail = saved_ecc_layout->oobavail;
470 }
471
472 return 0;
473 }
474 #endif /* CONFIG_KEYSTONE_RBL_NAND */
475
nand_davinci_4bit_enable_hwecc(struct mtd_info * mtd,int mode)476 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
477 {
478 u32 val;
479
480 switch (mode) {
481 case NAND_ECC_WRITE:
482 case NAND_ECC_READ:
483 /*
484 * Start a new ECC calculation for reading or writing 512 bytes
485 * of data.
486 */
487 val = __raw_readl(&davinci_emif_regs->nandfcr);
488 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
489 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
490 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
491 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
492 __raw_writel(val, &davinci_emif_regs->nandfcr);
493 break;
494 case NAND_ECC_READSYN:
495 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
496 break;
497 default:
498 break;
499 }
500 }
501
nand_davinci_4bit_readecc(struct mtd_info * mtd,unsigned int ecc[4])502 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
503 {
504 int i;
505
506 for (i = 0; i < 4; i++) {
507 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
508 NAND_4BITECC_MASK;
509 }
510
511 return 0;
512 }
513
nand_davinci_4bit_calculate_ecc(struct mtd_info * mtd,const uint8_t * dat,uint8_t * ecc_code)514 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
515 const uint8_t *dat,
516 uint8_t *ecc_code)
517 {
518 unsigned int hw_4ecc[4];
519 unsigned int i;
520
521 nand_davinci_4bit_readecc(mtd, hw_4ecc);
522
523 /*Convert 10 bit ecc value to 8 bit */
524 for (i = 0; i < 2; i++) {
525 unsigned int hw_ecc_low = hw_4ecc[i * 2];
526 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
527
528 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
529 *ecc_code++ = hw_ecc_low & 0xFF;
530
531 /*
532 * Take 2 bits as LSB bits from val1 (count1=0) or val5
533 * (count1=1) and 6 bits from val2 (count1=0) or
534 * val5 (count1=1)
535 */
536 *ecc_code++ =
537 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
538
539 /*
540 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
541 * 4 bits from val3 (count1=0) or val6 (count1=1)
542 */
543 *ecc_code++ =
544 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
545
546 /*
547 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
548 * 2 bits from val4 (count1=0) or val7 (count1=1)
549 */
550 *ecc_code++ =
551 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
552
553 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
554 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
555 }
556
557 return 0;
558 }
559
nand_davinci_4bit_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)560 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
561 uint8_t *read_ecc, uint8_t *calc_ecc)
562 {
563 int i;
564 unsigned int hw_4ecc[4];
565 unsigned int iserror;
566 unsigned short *ecc16;
567 unsigned int numerrors, erroraddress, errorvalue;
568 u32 val;
569
570 /*
571 * Check for an ECC where all bytes are 0xFF. If this is the case, we
572 * will assume we are looking at an erased page and we should ignore
573 * the ECC.
574 */
575 for (i = 0; i < 10; i++) {
576 if (read_ecc[i] != 0xFF)
577 break;
578 }
579 if (i == 10)
580 return 0;
581
582 /* Convert 8 bit in to 10 bit */
583 ecc16 = (unsigned short *)&read_ecc[0];
584
585 /*
586 * Write the parity values in the NAND Flash 4-bit ECC Load register.
587 * Write each parity value one at a time starting from 4bit_ecc_val8
588 * to 4bit_ecc_val1.
589 */
590
591 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
592 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
593 &davinci_emif_regs->nand4biteccload);
594
595 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
596 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
597 &davinci_emif_regs->nand4biteccload);
598
599 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
600 __raw_writel((ecc16[3] >> 2) & 0x3FF,
601 &davinci_emif_regs->nand4biteccload);
602
603 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
604 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
605 &davinci_emif_regs->nand4biteccload);
606
607 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
608 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
609 &davinci_emif_regs->nand4biteccload);
610
611 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
612 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
613 &davinci_emif_regs->nand4biteccload);
614
615 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
616 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
617 &davinci_emif_regs->nand4biteccload);
618
619 /* Take 10 bits from 0th and 1st bytes */
620 __raw_writel((ecc16[0]) & 0x3FF,
621 &davinci_emif_regs->nand4biteccload);
622
623 /*
624 * Perform a dummy read to the EMIF Revision Code and Status register.
625 * This is required to ensure time for syndrome calculation after
626 * writing the ECC values in previous step.
627 */
628
629 val = __raw_readl(&davinci_emif_regs->nandfsr);
630
631 /*
632 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
633 * A syndrome value of 0 means no bit errors. If the syndrome is
634 * non-zero then go further otherwise return.
635 */
636 nand_davinci_4bit_readecc(mtd, hw_4ecc);
637
638 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
639 return 0;
640
641 /*
642 * Clear any previous address calculation by doing a dummy read of an
643 * error address register.
644 */
645 val = __raw_readl(&davinci_emif_regs->nanderradd1);
646
647 /*
648 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
649 * register to 1.
650 */
651 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
652 &davinci_emif_regs->nandfcr);
653
654 /*
655 * Wait for the corr_state field (bits 8 to 11) in the
656 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
657 * Otherwise ECC calculation has not even begun and the next loop might
658 * fail because of a false positive!
659 */
660 i = NAND_TIMEOUT;
661 do {
662 val = __raw_readl(&davinci_emif_regs->nandfsr);
663 val &= 0xc00;
664 i--;
665 } while ((i > 0) && !val);
666
667 /*
668 * Wait for the corr_state field (bits 8 to 11) in the
669 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
670 */
671 i = NAND_TIMEOUT;
672 do {
673 val = __raw_readl(&davinci_emif_regs->nandfsr);
674 val &= 0xc00;
675 i--;
676 } while ((i > 0) && val);
677
678 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
679 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
680 iserror = iserror >> 8;
681
682 /*
683 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
684 * corrected (five or more errors). The number of errors
685 * calculated (err_num field) differs from the number of errors
686 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
687 * correction complete (errors on bit 8 or 9).
688 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
689 * complete (error exists).
690 */
691
692 if (iserror == ECC_STATE_NO_ERR) {
693 val = __raw_readl(&davinci_emif_regs->nanderrval1);
694 return 0;
695 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
696 val = __raw_readl(&davinci_emif_regs->nanderrval1);
697 return -EBADMSG;
698 }
699
700 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
701 & 0x3) + 1;
702
703 /* Read the error address, error value and correct */
704 for (i = 0; i < numerrors; i++) {
705 if (i > 1) {
706 erroraddress =
707 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
708 (16 * (i & 1))) & 0x3FF);
709 erroraddress = ((512 + 7) - erroraddress);
710 errorvalue =
711 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
712 (16 * (i & 1))) & 0xFF);
713 } else {
714 erroraddress =
715 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
716 (16 * (i & 1))) & 0x3FF);
717 erroraddress = ((512 + 7) - erroraddress);
718 errorvalue =
719 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
720 (16 * (i & 1))) & 0xFF);
721 }
722 /* xor the corrupt data with error value */
723 if (erroraddress < 512)
724 dat[erroraddress] ^= errorvalue;
725 }
726
727 return numerrors;
728 }
729 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
730
nand_davinci_dev_ready(struct mtd_info * mtd)731 static int nand_davinci_dev_ready(struct mtd_info *mtd)
732 {
733 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
734 }
735
davinci_nand_init(struct nand_chip * nand)736 static void davinci_nand_init(struct nand_chip *nand)
737 {
738 #if defined CONFIG_KEYSTONE_RBL_NAND
739 int i;
740 struct nand_ecclayout *layout;
741
742 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
743 layout->oobavail = 0;
744 for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
745 layout->oobfree[i].length; i++)
746 layout->oobavail += layout->oobfree[i].length;
747
748 nand->write_page = nand_davinci_write_page;
749 nand->ecc.read_page = nand_davinci_read_page_hwecc;
750 #endif
751 nand->chip_delay = 0;
752 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
753 nand->bbt_options |= NAND_BBT_USE_FLASH;
754 #endif
755 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
756 nand->options |= NAND_NO_SUBPAGE_WRITE;
757 #endif
758 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
759 nand->options |= NAND_BUSWIDTH_16;
760 #endif
761 #ifdef CONFIG_SYS_NAND_HW_ECC
762 nand->ecc.mode = NAND_ECC_HW;
763 nand->ecc.size = 512;
764 nand->ecc.bytes = 3;
765 nand->ecc.strength = 1;
766 nand->ecc.calculate = nand_davinci_calculate_ecc;
767 nand->ecc.correct = nand_davinci_correct_data;
768 nand->ecc.hwctl = nand_davinci_enable_hwecc;
769 #else
770 nand->ecc.mode = NAND_ECC_SOFT;
771 #endif /* CONFIG_SYS_NAND_HW_ECC */
772 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
773 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
774 nand->ecc.size = 512;
775 nand->ecc.bytes = 10;
776 nand->ecc.strength = 4;
777 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
778 nand->ecc.correct = nand_davinci_4bit_correct_data;
779 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
780 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
781 #endif
782 /* Set address of hardware control function */
783 nand->cmd_ctrl = nand_davinci_hwcontrol;
784
785 nand->read_buf = nand_davinci_read_buf;
786 nand->write_buf = nand_davinci_write_buf;
787
788 nand->dev_ready = nand_davinci_dev_ready;
789 }
790
791 #ifdef CONFIG_SYS_NAND_SELF_INIT
davinci_nand_probe(struct udevice * dev)792 static int davinci_nand_probe(struct udevice *dev)
793 {
794 struct nand_chip *nand = dev_get_priv(dev);
795 struct mtd_info *mtd = nand_to_mtd(nand);
796 int ret;
797
798 nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
799 nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
800
801 davinci_nand_init(nand);
802
803 ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
804 if (ret)
805 return ret;
806
807 return nand_register(0, mtd);
808 }
809
810 static const struct udevice_id davinci_nand_ids[] = {
811 { .compatible = "ti,davinci-nand" },
812 { }
813 };
814
815 U_BOOT_DRIVER(davinci_nand) = {
816 .name = "davinci-nand",
817 .id = UCLASS_MTD,
818 .of_match = davinci_nand_ids,
819 .probe = davinci_nand_probe,
820 .priv_auto = sizeof(struct nand_chip),
821 };
822
board_nand_init(void)823 void board_nand_init(void)
824 {
825 struct udevice *dev;
826 int ret;
827
828 ret = uclass_get_device_by_driver(UCLASS_MTD,
829 DM_DRIVER_GET(davinci_nand), &dev);
830 if (ret && ret != -ENODEV)
831 pr_err("Failed to initialize %s: %d\n", dev->name, ret);
832 }
833 #else
834 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
board_nand_init(struct nand_chip * chip)835 int board_nand_init(struct nand_chip *chip)
836 {
837 davinci_nand_init(chip);
838 return 0;
839 }
840 #endif /* CONFIG_SYS_NAND_SELF_INIT */
841