1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * FSL UPM NAND driver
4 *
5 * Copyright (C) 2007 MontaVista Software, Inc.
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <log.h>
12 #include <asm/io.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/fsl_upm.h>
18 #include <nand.h>
19
fsl_upm_start_pattern(struct fsl_upm * upm,u32 pat_offset)20 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
21 {
22 clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
23 (void)in_be32(upm->mxmr);
24 }
25
fsl_upm_end_pattern(struct fsl_upm * upm)26 static void fsl_upm_end_pattern(struct fsl_upm *upm)
27 {
28 clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
29
30 while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
31 eieio();
32 }
33
fsl_upm_run_pattern(struct fsl_upm * upm,int width,void __iomem * io_addr,u32 mar)34 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
35 void __iomem *io_addr, u32 mar)
36 {
37 out_be32(upm->mar, mar);
38 (void)in_be32(upm->mar);
39 switch (width) {
40 case 8:
41 out_8(io_addr, 0x0);
42 break;
43 case 16:
44 out_be16(io_addr, 0x0);
45 break;
46 case 32:
47 out_be32(io_addr, 0x0);
48 break;
49 }
50 }
51
fun_wait(struct fsl_upm_nand * fun)52 static void fun_wait(struct fsl_upm_nand *fun)
53 {
54 if (fun->dev_ready) {
55 while (!fun->dev_ready(fun->chip_nr))
56 debug("unexpected busy state\n");
57 } else {
58 /*
59 * If the R/B pin is not connected,
60 * a short delay is necessary.
61 */
62 udelay(1);
63 }
64 }
65
66 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
fun_select_chip(struct mtd_info * mtd,int chip_nr)67 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
68 {
69 struct nand_chip *chip = mtd_to_nand(mtd);
70 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
71
72 if (chip_nr >= 0) {
73 fun->chip_nr = chip_nr;
74 chip->IO_ADDR_R = chip->IO_ADDR_W =
75 fun->upm.io_addr + fun->chip_offset * chip_nr;
76 } else if (chip_nr == -1) {
77 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
78 }
79 }
80 #endif
81
fun_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)82 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
83 {
84 struct nand_chip *chip = mtd_to_nand(mtd);
85 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
86 void __iomem *io_addr;
87 u32 mar;
88
89 if (!(ctrl & fun->last_ctrl)) {
90 fsl_upm_end_pattern(&fun->upm);
91
92 if (cmd == NAND_CMD_NONE)
93 return;
94
95 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
96 }
97
98 if (ctrl & NAND_CTRL_CHANGE) {
99 if (ctrl & NAND_ALE)
100 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
101 else if (ctrl & NAND_CLE)
102 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
103 }
104
105 mar = cmd << (32 - fun->width);
106 io_addr = fun->upm.io_addr;
107 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
108 if (fun->chip_nr > 0) {
109 io_addr += fun->chip_offset * fun->chip_nr;
110 if (fun->upm_mar_chip_offset)
111 mar |= fun->upm_mar_chip_offset * fun->chip_nr;
112 }
113 #endif
114 fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
115
116 /*
117 * Some boards/chips needs this. At least the MPC8360E-RDK
118 * needs it. Probably weird chip, because I don't see any
119 * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
120 * here are 0-2 unexpected busy states per block read.
121 */
122 if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
123 fun_wait(fun);
124 }
125
upm_nand_read_byte(struct mtd_info * mtd)126 static u8 upm_nand_read_byte(struct mtd_info *mtd)
127 {
128 struct nand_chip *chip = mtd_to_nand(mtd);
129
130 return in_8(chip->IO_ADDR_R);
131 }
132
upm_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)133 static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
134 {
135 int i;
136 struct nand_chip *chip = mtd_to_nand(mtd);
137 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
138
139 for (i = 0; i < len; i++) {
140 out_8(chip->IO_ADDR_W, buf[i]);
141 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
142 fun_wait(fun);
143 }
144
145 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
146 fun_wait(fun);
147 }
148
upm_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)149 static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
150 {
151 int i;
152 struct nand_chip *chip = mtd_to_nand(mtd);
153
154 for (i = 0; i < len; i++)
155 buf[i] = in_8(chip->IO_ADDR_R);
156 }
157
nand_dev_ready(struct mtd_info * mtd)158 static int nand_dev_ready(struct mtd_info *mtd)
159 {
160 struct nand_chip *chip = mtd_to_nand(mtd);
161 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
162
163 return fun->dev_ready(fun->chip_nr);
164 }
165
fsl_upm_nand_init(struct nand_chip * chip,struct fsl_upm_nand * fun)166 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
167 {
168 if (fun->width != 8 && fun->width != 16 && fun->width != 32)
169 return -ENOSYS;
170
171 fun->last_ctrl = NAND_CLE;
172
173 nand_set_controller_data(chip, fun);
174 chip->chip_delay = fun->chip_delay;
175 chip->ecc.mode = NAND_ECC_SOFT;
176 chip->cmd_ctrl = fun_cmd_ctrl;
177 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
178 chip->select_chip = fun_select_chip;
179 #endif
180 chip->read_byte = upm_nand_read_byte;
181 chip->read_buf = upm_nand_read_buf;
182 chip->write_buf = upm_nand_write_buf;
183 if (fun->dev_ready)
184 chip->dev_ready = nand_dev_ready;
185
186 return 0;
187 }
188