1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * LPC32xx MLC NAND flash controller driver
4 *
5 * (C) Copyright 2014 3ADEV <http://3adev.com>
6 * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
7 *
8 * NOTE:
9 *
10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11 * covering in- and out-of-band data together. Therefore, in- and out-
12 * of-band data must be written together in order to have a valid ECC.
13 *
14 * Consequently, pages with meaningful in-band data are written with
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
17 *
18 * Therefore, code which reads such late-written out-of-band data
19 * should not rely on the ECC validity.
20 */
21
22 #include <common.h>
23 #include <nand.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <linux/mtd/rawnand.h>
27 #include <asm/io.h>
28 #include <nand.h>
29 #include <asm/arch/clk.h>
30 #include <asm/arch/sys_proto.h>
31
32 /*
33 * MLC NAND controller registers.
34 */
35 struct lpc32xx_nand_mlc_registers {
36 u8 buff[32768]; /* controller's serial data buffer */
37 u8 data[32768]; /* NAND's raw data buffer */
38 u32 cmd;
39 u32 addr;
40 u32 ecc_enc_reg;
41 u32 ecc_dec_reg;
42 u32 ecc_auto_enc_reg;
43 u32 ecc_auto_dec_reg;
44 u32 rpr;
45 u32 wpr;
46 u32 rubp;
47 u32 robp;
48 u32 sw_wp_add_low;
49 u32 sw_wp_add_hig;
50 u32 icr;
51 u32 time_reg;
52 u32 irq_mr;
53 u32 irq_sr;
54 u32 lock_pr;
55 u32 isr;
56 u32 ceh;
57 };
58
59 /* LOCK_PR register defines */
60 #define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */
61
62 /* ICR defines */
63 #define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */
64 #define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
65
66 /* CEH defines */
67 #define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */
68
69 /* ISR register defines */
70 #define ISR_NAND_READY 0x00000001
71 #define ISR_CONTROLLER_READY 0x00000002
72 #define ISR_ECC_READY 0x00000004
73 #define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
74 #define ISR_DECODER_FAILURE 0x00000040
75 #define ISR_DECODER_ERROR 0x00000008
76
77 /* time-out for NAND chip / controller loops, in us */
78 #define LPC32X_NAND_TIMEOUT 5000
79
80 /*
81 * There is a single instance of the NAND MLC controller
82 */
83
84 static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
85 = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
86
87 #if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
88 #define CONFIG_SYS_MAX_NAND_CHIPS 1
89 #endif
90
91 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
92
93 /**
94 * OOB data in each small page are 6 'free' then 10 ECC bytes.
95 * To make things easier, when reading large pages, the four pages'
96 * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
97 * while the the four ECC bytes are groupe in its last 40 bytes.
98 *
99 * The struct below represents how free vs ecc oob bytes are stored
100 * in the buffer.
101 *
102 * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
103 */
104
105 struct lpc32xx_oob {
106 struct {
107 uint8_t free_oob_bytes[6];
108 } free[4];
109 struct {
110 uint8_t ecc_oob_bytes[10];
111 } ecc[4];
112 };
113
114 /*
115 * Initialize the controller
116 */
117
lpc32xx_nand_init(void)118 static void lpc32xx_nand_init(void)
119 {
120 unsigned int clk;
121
122 /* Configure controller for no software write protection, x8 bus
123 width, large block device, and 4 address words */
124
125 /* unlock controller registers with magic key */
126 writel(LOCK_PR_UNLOCK_KEY,
127 &lpc32xx_nand_mlc_registers->lock_pr);
128
129 /* enable large blocks and large NANDs */
130 writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
131 &lpc32xx_nand_mlc_registers->icr);
132
133 /* Make sure MLC interrupts are disabled */
134 writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
135
136 /* Normal chip enable operation */
137 writel(CEH_NORMAL_CE,
138 &lpc32xx_nand_mlc_registers->ceh);
139
140 /* Setup NAND timing */
141 clk = get_hclk_clk_rate();
142
143 writel(
144 clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
145 clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
146 clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
147 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
148 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
149 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
150 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
151 &lpc32xx_nand_mlc_registers->time_reg);
152 }
153
154 #if !defined(CONFIG_SPL_BUILD)
155
156 /**
157 * lpc32xx_cmd_ctrl - write command to either cmd or data register
158 */
159
lpc32xx_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)160 static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
161 unsigned int ctrl)
162 {
163 if (cmd == NAND_CMD_NONE)
164 return;
165
166 if (ctrl & NAND_CLE)
167 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
168 else if (ctrl & NAND_ALE)
169 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
170 }
171
172 /**
173 * lpc32xx_read_byte - read a byte from the NAND
174 * @mtd: MTD device structure
175 */
176
lpc32xx_read_byte(struct mtd_info * mtd)177 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
178 {
179 return readb(&lpc32xx_nand_mlc_registers->data);
180 }
181
182 /**
183 * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
184 * @mtd: MTD device structure
185 * @mode: mode to set the ECC HW to.
186 */
187
lpc32xx_dev_ready(struct mtd_info * mtd)188 static int lpc32xx_dev_ready(struct mtd_info *mtd)
189 {
190 /* means *controller* ready for us */
191 int status = readl(&lpc32xx_nand_mlc_registers->isr);
192 return status & ISR_CONTROLLER_READY;
193 }
194
195 /**
196 * ECC layout -- this is needed whatever ECC mode we are using.
197 * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
198 * To make U-Boot's life easier, we pack 'useable' OOB at the
199 * front and R/S ECC at the back.
200 */
201
202 static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
203 .eccbytes = 40,
204 .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
205 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
206 44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
207 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
208 },
209 .oobfree = {
210 /* bytes 0 and 1 are used for the bad block marker */
211 {
212 .offset = 2,
213 .length = 22
214 },
215 }
216 };
217
218 /**
219 * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
220 * @mtd: mtd info structure
221 * @chip: nand chip info structure
222 * @buf: buffer to store read data
223 * @oob_required: caller requires OOB data read to chip->oob_poi
224 * @page: page number to read
225 *
226 * Use large block Auto Decode Read Mode(1) as described in User Manual
227 * section 8.6.2.1.
228 *
229 * The initial Read Mode and Read Start commands are sent by the caller.
230 *
231 * ECC will be false if out-of-band data has been updated since in-band
232 * data was initially written.
233 */
234
lpc32xx_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)235 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
236 struct nand_chip *chip, uint8_t *buf, int oob_required,
237 int page)
238 {
239 unsigned int i, status, timeout, err, max_bitflips = 0;
240 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
241
242 /* go through all four small pages */
243 for (i = 0; i < 4; i++) {
244 /* start auto decode (reads 528 NAND bytes) */
245 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
246 /* wait for controller to return to ready state */
247 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
248 status = readl(&lpc32xx_nand_mlc_registers->isr);
249 if (status & ISR_CONTROLLER_READY)
250 break;
251 udelay(1);
252 }
253 /* if decoder failed, return failure */
254 if (status & ISR_DECODER_FAILURE)
255 return -1;
256 /* keep count of maximum bitflips performed */
257 if (status & ISR_DECODER_ERROR) {
258 err = ISR_DECODER_ERRORS(status);
259 if (err > max_bitflips)
260 max_bitflips = err;
261 }
262 /* copy first 512 bytes into buffer */
263 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
264 /* copy next 6 bytes at front of OOB buffer */
265 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
266 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
267 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
268 }
269 return max_bitflips;
270 }
271
272 /**
273 * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
274 * @mtd: mtd info structure
275 * @chip: nand chip info structure
276 * @buf: buffer to store read data
277 * @oob_required: caller requires OOB data read to chip->oob_poi
278 * @page: page number to read
279 *
280 * Read NAND directly; can read pages with invalid ECC.
281 */
282
lpc32xx_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)283 static int lpc32xx_read_page_raw(struct mtd_info *mtd,
284 struct nand_chip *chip, uint8_t *buf, int oob_required,
285 int page)
286 {
287 unsigned int i, status, timeout;
288 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
289
290 /* when we get here we've already had the Read Mode(1) */
291
292 /* go through all four small pages */
293 for (i = 0; i < 4; i++) {
294 /* wait for NAND to return to ready state */
295 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
296 status = readl(&lpc32xx_nand_mlc_registers->isr);
297 if (status & ISR_NAND_READY)
298 break;
299 udelay(1);
300 }
301 /* if NAND stalled, return failure */
302 if (!(status & ISR_NAND_READY))
303 return -1;
304 /* copy first 512 bytes into buffer */
305 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
306 /* copy next 6 bytes at front of OOB buffer */
307 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
308 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
309 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
310 }
311 return 0;
312 }
313
314 /**
315 * lpc32xx_read_oob - read out-of-band data
316 * @mtd: mtd info structure
317 * @chip: nand chip info structure
318 * @page: page number to read
319 *
320 * Read out-of-band data. User Manual section 8.6.4 suggests using Read
321 * Mode(3) which the controller will turn into a Read Mode(1) internally
322 * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
323 * directly.
324 *
325 * ECC covers in- and out-of-band data and was written when out-of-band
326 * data was blank. Therefore, if the out-of-band being read here is not
327 * blank, then the ECC will be false and the read will return bitflips,
328 * even in case of ECC failure where we will return 5 bitflips. The
329 * caller should be prepared to handle this.
330 */
331
lpc32xx_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)332 static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
333 int page)
334 {
335 unsigned int i, status, timeout, err, max_bitflips = 0;
336 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
337
338 /* No command was sent before calling read_oob() so send one */
339
340 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
341
342 /* go through all four small pages */
343 for (i = 0; i < 4; i++) {
344 /* start auto decode (reads 528 NAND bytes) */
345 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
346 /* wait for controller to return to ready state */
347 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
348 status = readl(&lpc32xx_nand_mlc_registers->isr);
349 if (status & ISR_CONTROLLER_READY)
350 break;
351 udelay(1);
352 }
353 /* if decoder failure, count 'one too many' bitflips */
354 if (status & ISR_DECODER_FAILURE)
355 max_bitflips = 5;
356 /* keep count of maximum bitflips performed */
357 if (status & ISR_DECODER_ERROR) {
358 err = ISR_DECODER_ERRORS(status);
359 if (err > max_bitflips)
360 max_bitflips = err;
361 }
362 /* set read pointer to OOB area */
363 writel(0, &lpc32xx_nand_mlc_registers->robp);
364 /* copy next 6 bytes at front of OOB buffer */
365 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
366 /* copy next 10 bytes (R/S ECC) at back of OOB buffer */
367 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
368 }
369 return max_bitflips;
370 }
371
372 /**
373 * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
374 * @mtd: mtd info structure
375 * @chip: nand chip info structure
376 * @buf: data buffer
377 * @oob_required: must write chip->oob_poi to OOB
378 *
379 * Use large block Auto Encode as per User Manual section 8.6.4.
380 *
381 * The initial Write Serial Input and final Auto Program commands are
382 * sent by the caller.
383 */
384
lpc32xx_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)385 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
386 struct nand_chip *chip, const uint8_t *buf, int oob_required,
387 int page)
388 {
389 unsigned int i, status, timeout;
390 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
391
392 /* when we get here we've already had the SEQIN */
393 for (i = 0; i < 4; i++) {
394 /* start encode (expects 518 writes to buff) */
395 writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
396 /* copy first 512 bytes from buffer */
397 memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
398 /* copy next 6 bytes from OOB buffer -- excluding ECC */
399 memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
400 /* wait for ECC to return to ready state */
401 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
402 status = readl(&lpc32xx_nand_mlc_registers->isr);
403 if (status & ISR_ECC_READY)
404 break;
405 udelay(1);
406 }
407 /* if ECC stalled, return failure */
408 if (!(status & ISR_ECC_READY))
409 return -1;
410 /* Trigger auto encode (writes 528 bytes to NAND) */
411 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
412 /* wait for controller to return to ready state */
413 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
414 status = readl(&lpc32xx_nand_mlc_registers->isr);
415 if (status & ISR_CONTROLLER_READY)
416 break;
417 udelay(1);
418 }
419 /* if controller stalled, return error */
420 if (!(status & ISR_CONTROLLER_READY))
421 return -1;
422 }
423 return 0;
424 }
425
426 /**
427 * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
428 * @mtd: mtd info structure
429 * @chip: nand chip info structure
430 * @buf: buffer to store read data
431 * @oob_required: caller requires OOB data read to chip->oob_poi
432 * @page: page number to read
433 *
434 * Use large block write but without encode.
435 *
436 * The initial Write Serial Input and final Auto Program commands are
437 * sent by the caller.
438 *
439 * This function will write the full out-of-band data, including the
440 * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
441 */
442
lpc32xx_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)443 static int lpc32xx_write_page_raw(struct mtd_info *mtd,
444 struct nand_chip *chip, const uint8_t *buf, int oob_required,
445 int page)
446 {
447 unsigned int i;
448 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
449
450 /* when we get here we've already had the Read Mode(1) */
451 for (i = 0; i < 4; i++) {
452 /* copy first 512 bytes from buffer */
453 memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
454 /* copy next 6 bytes into OOB buffer -- excluding ECC */
455 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
456 /* copy next 10 bytes into OOB buffer -- that is 'ECC' */
457 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
458 }
459 return 0;
460 }
461
462 /**
463 * lpc32xx_write_oob - write out-of-band data
464 * @mtd: mtd info structure
465 * @chip: nand chip info structure
466 * @page: page number to read
467 *
468 * Since ECC covers in- and out-of-band data, writing out-of-band data
469 * with ECC will render the page ECC wrong -- or, if the page was blank,
470 * then it will produce a good ECC but a later in-band data write will
471 * render it wrong.
472 *
473 * Therefore, do not compute or write any ECC, and always return success.
474 *
475 * This implies that we do four writes, since non-ECC out-of-band data
476 * are not contiguous in a large page.
477 */
478
lpc32xx_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)479 static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
480 int page)
481 {
482 /* update oob on all 4 subpages in sequence */
483 unsigned int i, status, timeout;
484 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
485
486 for (i = 0; i < 4; i++) {
487 /* start data input */
488 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
489 /* copy 6 non-ECC out-of-band bytes directly into NAND */
490 memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
491 /* program page */
492 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
493 /* wait for NAND to return to ready state */
494 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
495 status = readl(&lpc32xx_nand_mlc_registers->isr);
496 if (status & ISR_NAND_READY)
497 break;
498 udelay(1);
499 }
500 /* if NAND stalled, return error */
501 if (!(status & ISR_NAND_READY))
502 return -1;
503 }
504 return 0;
505 }
506
507 /**
508 * lpc32xx_waitfunc - wait until a command is done
509 * @mtd: MTD device structure
510 * @chip: NAND chip structure
511 *
512 * Wait for controller and FLASH to both be ready.
513 */
514
lpc32xx_waitfunc(struct mtd_info * mtd,struct nand_chip * chip)515 static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
516 {
517 int status;
518 unsigned int timeout;
519 /* wait until both controller and NAND are ready */
520 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
521 status = readl(&lpc32xx_nand_mlc_registers->isr);
522 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
523 == (ISR_CONTROLLER_READY || ISR_NAND_READY))
524 break;
525 udelay(1);
526 }
527 /* if controller or NAND stalled, return error */
528 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
529 != (ISR_CONTROLLER_READY || ISR_NAND_READY))
530 return -1;
531 /* write NAND status command */
532 writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
533 /* read back status and return it */
534 return readb(&lpc32xx_nand_mlc_registers->data);
535 }
536
537 /*
538 * We are self-initializing, so we need our own chip struct
539 */
540
541 static struct nand_chip lpc32xx_chip;
542
543 /*
544 * Initialize the controller
545 */
546
board_nand_init(void)547 void board_nand_init(void)
548 {
549 struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
550 int ret;
551
552 /* Set all BOARDSPECIFIC (actually core-specific) fields */
553
554 lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
555 lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
556 lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
557 /* do not set init_size: nand_base.c will read sizes from chip */
558 lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
559 /* do not set setup_read_retry: this is NAND-chip-specific */
560 /* do not set chip_delay: we have dev_ready defined. */
561 lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
562
563 /* Set needed ECC fields */
564
565 lpc32xx_chip.ecc.mode = NAND_ECC_HW;
566 lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
567 lpc32xx_chip.ecc.size = 512;
568 lpc32xx_chip.ecc.bytes = 10;
569 lpc32xx_chip.ecc.strength = 4;
570 lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
571 lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
572 lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
573 lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
574 lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
575 lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
576 lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
577
578 lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
579
580 /* BBT options: read from last two pages */
581 lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
582 | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
583 | NAND_BBT_WRITE;
584
585 /* Initialize NAND interface */
586 lpc32xx_nand_init();
587
588 /* identify chip */
589 ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
590 if (ret) {
591 pr_err("nand_scan_ident returned %i", ret);
592 return;
593 }
594
595 /* finish scanning the chip */
596 ret = nand_scan_tail(mtd);
597 if (ret) {
598 pr_err("nand_scan_tail returned %i", ret);
599 return;
600 }
601
602 /* chip is good, register it */
603 ret = nand_register(0, mtd);
604 if (ret)
605 pr_err("nand_register returned %i", ret);
606 }
607
608 #else /* defined(CONFIG_SPL_BUILD) */
609
nand_init(void)610 void nand_init(void)
611 {
612 /* enable NAND controller */
613 lpc32xx_mlc_nand_init();
614 /* initialize NAND controller */
615 lpc32xx_nand_init();
616 }
617
nand_deselect(void)618 void nand_deselect(void)
619 {
620 /* nothing to do, but SPL requires this function */
621 }
622
read_single_page(uint8_t * dest,int page,struct lpc32xx_oob * oob)623 static int read_single_page(uint8_t *dest, int page,
624 struct lpc32xx_oob *oob)
625 {
626 int status, i, timeout, err, max_bitflips = 0;
627
628 /* enter read mode */
629 writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
630 /* send column (lsb then MSB) and page (lsb to MSB) */
631 writel(0, &lpc32xx_nand_mlc_registers->addr);
632 writel(0, &lpc32xx_nand_mlc_registers->addr);
633 writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
634 writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
635 writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
636 /* start reading */
637 writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
638
639 /* large page auto decode read */
640 for (i = 0; i < 4; i++) {
641 /* start auto decode (reads 528 NAND bytes) */
642 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
643 /* wait for controller to return to ready state */
644 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
645 status = readl(&lpc32xx_nand_mlc_registers->isr);
646 if (status & ISR_CONTROLLER_READY)
647 break;
648 udelay(1);
649 }
650 /* if controller stalled, return error */
651 if (!(status & ISR_CONTROLLER_READY))
652 return -1;
653 /* if decoder failure, return error */
654 if (status & ISR_DECODER_FAILURE)
655 return -1;
656 /* keep count of maximum bitflips performed */
657 if (status & ISR_DECODER_ERROR) {
658 err = ISR_DECODER_ERRORS(status);
659 if (err > max_bitflips)
660 max_bitflips = err;
661 }
662 /* copy first 512 bytes into buffer */
663 memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
664 /* copy next 6 bytes bytes into OOB buffer */
665 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
666 }
667 return max_bitflips;
668 }
669
670 /*
671 * Load U-Boot signed image.
672 * This loads an image from NAND, skipping bad blocks.
673 * A block is declared bad if at least one of its readable pages has
674 * a bad block marker in its OOB at position 0.
675 * If all pages ion a block are unreadable, the block is considered
676 * bad (i.e., assumed not to be part of the image) and skipped.
677 *
678 * IMPORTANT NOTE:
679 *
680 * If the first block of the image is fully unreadable, it will be
681 * ignored and skipped as if it had been marked bad. If it was not
682 * actually marked bad at the time of writing the image, the resulting
683 * image loaded will lack a header and magic number. It could thus be
684 * considered as a raw, headerless, image and SPL might erroneously
685 * jump into it.
686 *
687 * In order to avoid this risk, LPC32XX-based boards which use this
688 * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
689 */
690
691 #define BYTES_PER_PAGE 2048
692 #define PAGES_PER_BLOCK 64
693 #define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
694 #define PAGES_PER_CHIP_MAX 524288
695
nand_spl_load_image(uint32_t offs,unsigned int size,void * dst)696 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
697 {
698 int bytes_left = size;
699 int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
700 int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
701 int block = 0;
702 int page = offs / BYTES_PER_PAGE;
703 /* perform reads block by block */
704 while (blocks_left) {
705 /* compute first page number to read */
706 void *block_page_dst = dst;
707 /* read at most one block, possibly less */
708 int block_bytes_left = bytes_left;
709 if (block_bytes_left > BYTES_PER_BLOCK)
710 block_bytes_left = BYTES_PER_BLOCK;
711 /* keep track of good, failed, and "bad" pages */
712 int block_pages_good = 0;
713 int block_pages_bad = 0;
714 int block_pages_err = 0;
715 /* we shall read a full block of pages, maybe less */
716 int block_pages_left = pages_left;
717 if (block_pages_left > PAGES_PER_BLOCK)
718 block_pages_left = PAGES_PER_BLOCK;
719 int block_pages = block_pages_left;
720 int block_page = page;
721 /* while pages are left and the block is not known as bad */
722 while ((block_pages > 0) && (block_pages_bad == 0)) {
723 /* we will read OOB, too, for bad block markers */
724 struct lpc32xx_oob oob;
725 /* read page */
726 int res = read_single_page(block_page_dst, block_page,
727 &oob);
728 /* count readable pages */
729 if (res >= 0) {
730 /* this page is good */
731 block_pages_good++;
732 /* this page is bad */
733 if ((oob.free[0].free_oob_bytes[0] != 0xff)
734 | (oob.free[0].free_oob_bytes[1] != 0xff))
735 block_pages_bad++;
736 } else
737 /* count errors */
738 block_pages_err++;
739 /* we're done with this page */
740 block_page++;
741 block_page_dst += BYTES_PER_PAGE;
742 if (block_pages)
743 block_pages--;
744 }
745 /* a fully unreadable block is considered bad */
746 if (block_pages_good == 0)
747 block_pages_bad = block_pages_err;
748 /* errors are fatal only in good blocks */
749 if ((block_pages_err > 0) && (block_pages_bad == 0))
750 return -1;
751 /* we keep reads only of good blocks */
752 if (block_pages_bad == 0) {
753 dst += block_bytes_left;
754 bytes_left -= block_bytes_left;
755 pages_left -= block_pages_left;
756 blocks_left--;
757 }
758 /* good or bad, we're done with this block */
759 block++;
760 page += PAGES_PER_BLOCK;
761 }
762
763 /* report success */
764 return 0;
765 }
766
767 #endif /* CONFIG_SPL_BUILD */
768