1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Magnus Lilja <lilja.magnus@gmail.com>
5 *
6 * (C) Copyright 2008
7 * Maxim Artamonov, <scn1874 at yandex.ru>
8 *
9 * (C) Copyright 2006-2008
10 * Stefan Roese, DENX Software Engineering, sr at denx.de.
11 */
12
13 #include <common.h>
14 #include <hang.h>
15 #include <nand.h>
16 #include <linux/mtd/rawnand.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/io.h>
19 #include "mxc_nand.h"
20
21 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
22 static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
23 #elif defined(MXC_NFC_V3_2)
24 static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
25 static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
26 #endif
27
nfc_wait_ready(void)28 static void nfc_wait_ready(void)
29 {
30 uint32_t tmp;
31
32 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
33 while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
34 ;
35
36 /* Reset interrupt flag */
37 tmp = readnfc(&nfc->config2);
38 tmp &= ~NFC_V1_V2_CONFIG2_INT;
39 writenfc(tmp, &nfc->config2);
40 #elif defined(MXC_NFC_V3_2)
41 while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
42 ;
43
44 /* Reset interrupt flag */
45 tmp = readnfc(&nfc_ip->ipc);
46 tmp &= ~NFC_V3_IPC_INT;
47 writenfc(tmp, &nfc_ip->ipc);
48 #endif
49 }
50
nfc_nand_init(void)51 static void nfc_nand_init(void)
52 {
53 #if defined(MXC_NFC_V3_2)
54 int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
55 int tmp;
56
57 tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
58 NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
59 NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
60 NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
61 NFC_V3_CONFIG2_ONE_CYCLE;
62 if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
63 tmp |= NFC_V3_CONFIG2_PS_4096;
64 else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
65 tmp |= NFC_V3_CONFIG2_PS_2048;
66 else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
67 tmp |= NFC_V3_CONFIG2_PS_512;
68 /*
69 * if spare size is larger that 16 bytes per 512 byte hunk
70 * then use 8 symbol correction instead of 4
71 */
72 if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
73 tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
74 else
75 tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
76 writenfc(tmp, &nfc_ip->config2);
77
78 tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
79 NFC_V3_CONFIG3_NO_SDMA |
80 NFC_V3_CONFIG3_RBB_MODE |
81 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
82 NFC_V3_CONFIG3_ADD_OP(0);
83 #ifndef CONFIG_SYS_NAND_BUSWIDTH_16
84 tmp |= NFC_V3_CONFIG3_FW8;
85 #endif
86 writenfc(tmp, &nfc_ip->config3);
87
88 writenfc(0, &nfc_ip->delay_line);
89 #elif defined(MXC_NFC_V2_1)
90 int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
91 int config1;
92
93 writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
94
95 /* unlocking RAM Buff */
96 writenfc(0x2, &nfc->config);
97
98 /* hardware ECC checking and correct */
99 config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
100 NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
101 NFC_V2_CONFIG1_FP_INT;
102 /*
103 * if spare size is larger that 16 bytes per 512 byte hunk
104 * then use 8 symbol correction instead of 4
105 */
106 if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
107 config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
108 else
109 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
110 writenfc(config1, &nfc->config1);
111 #elif defined(MXC_NFC_V1)
112 /* unlocking RAM Buff */
113 writenfc(0x2, &nfc->config);
114
115 /* hardware ECC checking and correct */
116 writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
117 &nfc->config1);
118 #endif
119 }
120
nfc_nand_command(unsigned short command)121 static void nfc_nand_command(unsigned short command)
122 {
123 writenfc(command, &nfc->flash_cmd);
124 writenfc(NFC_CMD, &nfc->operation);
125 nfc_wait_ready();
126 }
127
nfc_nand_address(unsigned short address)128 static void nfc_nand_address(unsigned short address)
129 {
130 writenfc(address, &nfc->flash_addr);
131 writenfc(NFC_ADDR, &nfc->operation);
132 nfc_wait_ready();
133 }
134
nfc_nand_page_address(unsigned int page_address)135 static void nfc_nand_page_address(unsigned int page_address)
136 {
137 unsigned int page_count;
138
139 nfc_nand_address(0x00);
140
141 /* code only for large page flash */
142 if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
143 nfc_nand_address(0x00);
144
145 page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
146
147 if (page_address <= page_count) {
148 page_count--; /* transform 0x01000000 to 0x00ffffff */
149 do {
150 nfc_nand_address(page_address & 0xff);
151 page_address = page_address >> 8;
152 page_count = page_count >> 8;
153 } while (page_count);
154 }
155
156 nfc_nand_address(0x00);
157 }
158
nfc_nand_data_output(void)159 static void nfc_nand_data_output(void)
160 {
161 #ifdef NAND_MXC_2K_MULTI_CYCLE
162 int i;
163 #endif
164
165 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
166 writenfc(0, &nfc->buf_addr);
167 #elif defined(MXC_NFC_V3_2)
168 int config1 = readnfc(&nfc->config1);
169 config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
170 writenfc(config1, &nfc->config1);
171 #endif
172 writenfc(NFC_OUTPUT, &nfc->operation);
173 nfc_wait_ready();
174 #ifdef NAND_MXC_2K_MULTI_CYCLE
175 /*
176 * This NAND controller requires multiple input commands
177 * for pages larger than 512 bytes.
178 */
179 for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
180 writenfc(i, &nfc->buf_addr);
181 writenfc(NFC_OUTPUT, &nfc->operation);
182 nfc_wait_ready();
183 }
184 #endif
185 }
186
nfc_nand_check_ecc(void)187 static int nfc_nand_check_ecc(void)
188 {
189 #if defined(MXC_NFC_V1)
190 u16 ecc_status = readw(&nfc->ecc_status_result);
191 return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
192 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
193 u32 ecc_status = readl(&nfc->ecc_status_result);
194 int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
195 int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
196 int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
197
198 do {
199 if ((ecc_status & 0xf) > err_limit)
200 return 1;
201 ecc_status >>= 4;
202 } while (--subpages);
203
204 return 0;
205 #endif
206 }
207
nfc_nand_read_page(unsigned int page_address)208 static void nfc_nand_read_page(unsigned int page_address)
209 {
210 /* read in first 0 buffer */
211 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
212 writenfc(0, &nfc->buf_addr);
213 #elif defined(MXC_NFC_V3_2)
214 int config1 = readnfc(&nfc->config1);
215 config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
216 writenfc(config1, &nfc->config1);
217 #endif
218 nfc_nand_command(NAND_CMD_READ0);
219 nfc_nand_page_address(page_address);
220
221 if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
222 nfc_nand_command(NAND_CMD_READSTART);
223
224 nfc_nand_data_output(); /* fill the main buffer 0 */
225 }
226
nfc_read_page(unsigned int page_address,unsigned char * buf)227 static int nfc_read_page(unsigned int page_address, unsigned char *buf)
228 {
229 int i;
230 u32 *src;
231 u32 *dst;
232
233 nfc_nand_read_page(page_address);
234
235 if (nfc_nand_check_ecc())
236 return -EBADMSG;
237
238 src = (u32 *)&nfc->main_area[0][0];
239 dst = (u32 *)buf;
240
241 /* main copy loop from NAND-buffer to SDRAM memory */
242 for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
243 writel(readl(src), dst);
244 src++;
245 dst++;
246 }
247
248 return 0;
249 }
250
is_badblock(int pagenumber)251 static int is_badblock(int pagenumber)
252 {
253 int page = pagenumber;
254 u32 badblock;
255 u32 *src;
256
257 /* Check the first two pages for bad block markers */
258 for (page = pagenumber; page < pagenumber + 2; page++) {
259 nfc_nand_read_page(page);
260
261 src = (u32 *)&nfc->spare_area[0][0];
262
263 /*
264 * IMPORTANT NOTE: The nand flash controller uses a non-
265 * standard layout for large page devices. This can
266 * affect the position of the bad block marker.
267 */
268 /* Get the bad block marker */
269 badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
270 badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
271 badblock &= 0xff;
272
273 /* bad block marker verify */
274 if (badblock != 0xff)
275 return 1; /* potential bad block */
276 }
277
278 return 0;
279 }
280
nand_spl_load_image(uint32_t from,unsigned int size,void * buf)281 int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
282 {
283 int i;
284 unsigned int page;
285 unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
286 CONFIG_SYS_NAND_PAGE_SIZE;
287
288 nfc_nand_init();
289
290 /* Convert to page number */
291 page = from / CONFIG_SYS_NAND_PAGE_SIZE;
292 i = 0;
293
294 size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
295 while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
296 if (nfc_read_page(page, buf) < 0)
297 return -1;
298
299 page++;
300 i++;
301 buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
302
303 /*
304 * Check if we have crossed a block boundary, and if so
305 * check for bad block.
306 */
307 if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
308 /*
309 * Yes, new block. See if this block is good. If not,
310 * loop until we find a good block.
311 */
312 while (is_badblock(page)) {
313 page = page + CONFIG_SYS_NAND_PAGE_COUNT;
314 /* Check i we've reached the end of flash. */
315 if (page >= maxpages)
316 return -1;
317 }
318 }
319 }
320
321 return 0;
322 }
323
324 #ifndef CONFIG_SPL_FRAMEWORK
325 /*
326 * The main entry for NAND booting. It's necessary that SDRAM is already
327 * configured and available since this code loads the main U-Boot image
328 * from NAND into SDRAM and starts it from there.
329 */
nand_boot(void)330 __used void nand_boot(void)
331 {
332 __attribute__((noreturn)) void (*uboot)(void);
333
334 /*
335 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
336 * be aligned to full pages
337 */
338 if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
339 CONFIG_SYS_NAND_U_BOOT_SIZE,
340 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
341 /* Copy from NAND successful, start U-Boot */
342 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
343 uboot();
344 } else {
345 /* Unrecoverable error when copying from NAND */
346 hang();
347 }
348 }
349 #endif
350
nand_init(void)351 void nand_init(void) {}
nand_deselect(void)352 void nand_deselect(void) {}
353