1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) STMicroelectronics 2019
4 * Author: Christophe Kerello <christophe.kerello@st.com>
5 */
6
7 #define LOG_CATEGORY UCLASS_MTD
8
9 #include <common.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <nand.h>
14 #include <reset.h>
15 #include <dm/device_compat.h>
16 #include <linux/bitfield.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/iopoll.h>
21 #include <linux/ioport.h>
22 #include <linux/mtd/rawnand.h>
23
24 /* Bad block marker length */
25 #define FMC2_BBM_LEN 2
26
27 /* ECC step size */
28 #define FMC2_ECC_STEP_SIZE 512
29
30 /* Command delay */
31 #define FMC2_RB_DELAY_US 30
32
33 /* Max chip enable */
34 #define FMC2_MAX_CE 2
35
36 /* Timings */
37 #define FMC2_THIZ 1
38 #define FMC2_TIO 8000
39 #define FMC2_TSYNC 3000
40 #define FMC2_PCR_TIMING_MASK 0xf
41 #define FMC2_PMEM_PATT_TIMING_MASK 0xff
42
43 /* FMC2 Controller Registers */
44 #define FMC2_BCR1 0x0
45 #define FMC2_PCR 0x80
46 #define FMC2_SR 0x84
47 #define FMC2_PMEM 0x88
48 #define FMC2_PATT 0x8c
49 #define FMC2_HECCR 0x94
50 #define FMC2_BCHISR 0x254
51 #define FMC2_BCHICR 0x258
52 #define FMC2_BCHPBR1 0x260
53 #define FMC2_BCHPBR2 0x264
54 #define FMC2_BCHPBR3 0x268
55 #define FMC2_BCHPBR4 0x26c
56 #define FMC2_BCHDSR0 0x27c
57 #define FMC2_BCHDSR1 0x280
58 #define FMC2_BCHDSR2 0x284
59 #define FMC2_BCHDSR3 0x288
60 #define FMC2_BCHDSR4 0x28c
61
62 /* Register: FMC2_BCR1 */
63 #define FMC2_BCR1_FMC2EN BIT(31)
64
65 /* Register: FMC2_PCR */
66 #define FMC2_PCR_PWAITEN BIT(1)
67 #define FMC2_PCR_PBKEN BIT(2)
68 #define FMC2_PCR_PWID GENMASK(5, 4)
69 #define FMC2_PCR_PWID_BUSWIDTH_8 0
70 #define FMC2_PCR_PWID_BUSWIDTH_16 1
71 #define FMC2_PCR_ECCEN BIT(6)
72 #define FMC2_PCR_ECCALG BIT(8)
73 #define FMC2_PCR_TCLR GENMASK(12, 9)
74 #define FMC2_PCR_TCLR_DEFAULT 0xf
75 #define FMC2_PCR_TAR GENMASK(16, 13)
76 #define FMC2_PCR_TAR_DEFAULT 0xf
77 #define FMC2_PCR_ECCSS GENMASK(19, 17)
78 #define FMC2_PCR_ECCSS_512 1
79 #define FMC2_PCR_ECCSS_2048 3
80 #define FMC2_PCR_BCHECC BIT(24)
81 #define FMC2_PCR_WEN BIT(25)
82
83 /* Register: FMC2_SR */
84 #define FMC2_SR_NWRF BIT(6)
85
86 /* Register: FMC2_PMEM */
87 #define FMC2_PMEM_MEMSET GENMASK(7, 0)
88 #define FMC2_PMEM_MEMWAIT GENMASK(15, 8)
89 #define FMC2_PMEM_MEMHOLD GENMASK(23, 16)
90 #define FMC2_PMEM_MEMHIZ GENMASK(31, 24)
91 #define FMC2_PMEM_DEFAULT 0x0a0a0a0a
92
93 /* Register: FMC2_PATT */
94 #define FMC2_PATT_ATTSET GENMASK(7, 0)
95 #define FMC2_PATT_ATTWAIT GENMASK(15, 8)
96 #define FMC2_PATT_ATTHOLD GENMASK(23, 16)
97 #define FMC2_PATT_ATTHIZ GENMASK(31, 24)
98 #define FMC2_PATT_DEFAULT 0x0a0a0a0a
99
100 /* Register: FMC2_BCHISR */
101 #define FMC2_BCHISR_DERF BIT(1)
102 #define FMC2_BCHISR_EPBRF BIT(4)
103
104 /* Register: FMC2_BCHICR */
105 #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
106
107 /* Register: FMC2_BCHDSR0 */
108 #define FMC2_BCHDSR0_DUE BIT(0)
109 #define FMC2_BCHDSR0_DEF BIT(1)
110 #define FMC2_BCHDSR0_DEN GENMASK(7, 4)
111
112 /* Register: FMC2_BCHDSR1 */
113 #define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)
114 #define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)
115
116 /* Register: FMC2_BCHDSR2 */
117 #define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)
118 #define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)
119
120 /* Register: FMC2_BCHDSR3 */
121 #define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)
122 #define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)
123
124 /* Register: FMC2_BCHDSR4 */
125 #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
126 #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
127
128 #define FMC2_NSEC_PER_SEC 1000000000L
129
130 #define FMC2_TIMEOUT_5S 5000000
131
132 enum stm32_fmc2_ecc {
133 FMC2_ECC_HAM = 1,
134 FMC2_ECC_BCH4 = 4,
135 FMC2_ECC_BCH8 = 8
136 };
137
138 struct stm32_fmc2_timings {
139 u8 tclr;
140 u8 tar;
141 u8 thiz;
142 u8 twait;
143 u8 thold_mem;
144 u8 tset_mem;
145 u8 thold_att;
146 u8 tset_att;
147 };
148
149 struct stm32_fmc2_nand {
150 struct nand_chip chip;
151 struct stm32_fmc2_timings timings;
152 int ncs;
153 int cs_used[FMC2_MAX_CE];
154 };
155
to_fmc2_nand(struct nand_chip * chip)156 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
157 {
158 return container_of(chip, struct stm32_fmc2_nand, chip);
159 }
160
161 struct stm32_fmc2_nfc {
162 struct nand_hw_control base;
163 struct stm32_fmc2_nand nand;
164 struct nand_ecclayout ecclayout;
165 fdt_addr_t io_base;
166 fdt_addr_t data_base[FMC2_MAX_CE];
167 fdt_addr_t cmd_base[FMC2_MAX_CE];
168 fdt_addr_t addr_base[FMC2_MAX_CE];
169 struct clk clk;
170
171 u8 cs_assigned;
172 int cs_sel;
173 };
174
to_stm32_nfc(struct nand_hw_control * base)175 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
176 {
177 return container_of(base, struct stm32_fmc2_nfc, base);
178 }
179
stm32_fmc2_nfc_timings_init(struct nand_chip * chip)180 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
181 {
182 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
183 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
184 struct stm32_fmc2_timings *timings = &nand->timings;
185 u32 pmem, patt;
186
187 /* Set tclr/tar timings */
188 clrsetbits_le32(nfc->io_base + FMC2_PCR,
189 FMC2_PCR_TCLR | FMC2_PCR_TAR,
190 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
191 FIELD_PREP(FMC2_PCR_TAR, timings->tar));
192
193 /* Set tset/twait/thold/thiz timings in common bank */
194 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
195 pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
196 pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
197 pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
198 writel(pmem, nfc->io_base + FMC2_PMEM);
199
200 /* Set tset/twait/thold/thiz timings in attribut bank */
201 patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
202 patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
203 patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
204 patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
205 writel(patt, nfc->io_base + FMC2_PATT);
206 }
207
stm32_fmc2_nfc_setup(struct nand_chip * chip)208 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
209 {
210 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
211 u32 pcr = 0, pcr_mask;
212
213 /* Configure ECC algorithm (default configuration is Hamming) */
214 pcr_mask = FMC2_PCR_ECCALG;
215 pcr_mask |= FMC2_PCR_BCHECC;
216 if (chip->ecc.strength == FMC2_ECC_BCH8) {
217 pcr |= FMC2_PCR_ECCALG;
218 pcr |= FMC2_PCR_BCHECC;
219 } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
220 pcr |= FMC2_PCR_ECCALG;
221 }
222
223 /* Set buswidth */
224 pcr_mask |= FMC2_PCR_PWID;
225 if (chip->options & NAND_BUSWIDTH_16)
226 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
227
228 /* Set ECC sector size */
229 pcr_mask |= FMC2_PCR_ECCSS;
230 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
231
232 clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr);
233 }
234
stm32_fmc2_nfc_select_chip(struct mtd_info * mtd,int chipnr)235 static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
236 {
237 struct nand_chip *chip = mtd_to_nand(mtd);
238 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
239 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
240
241 if (chipnr < 0 || chipnr >= nand->ncs)
242 return;
243
244 if (nand->cs_used[chipnr] == nfc->cs_sel)
245 return;
246
247 nfc->cs_sel = nand->cs_used[chipnr];
248 chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel];
249 chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel];
250
251 stm32_fmc2_nfc_setup(chip);
252 stm32_fmc2_nfc_timings_init(chip);
253 }
254
stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc * nfc,bool set)255 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
256 bool set)
257 {
258 u32 pcr;
259
260 pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
261 FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
262
263 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr);
264 }
265
stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc * nfc,bool enable)266 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
267 {
268 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN,
269 enable ? FMC2_PCR_ECCEN : 0);
270 }
271
stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc * nfc)272 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
273 {
274 writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
275 }
276
stm32_fmc2_nfc_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)277 static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
278 unsigned int ctrl)
279 {
280 struct nand_chip *chip = mtd_to_nand(mtd);
281 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
282
283 if (cmd == NAND_CMD_NONE)
284 return;
285
286 if (ctrl & NAND_CLE) {
287 writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
288 return;
289 }
290
291 writeb(cmd, nfc->addr_base[nfc->cs_sel]);
292 }
293
294 /*
295 * Enable ECC logic and reset syndrome/parity bits previously calculated
296 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
297 */
stm32_fmc2_nfc_hwctl(struct mtd_info * mtd,int mode)298 static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
299 {
300 struct nand_chip *chip = mtd_to_nand(mtd);
301 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
302
303 stm32_fmc2_nfc_set_ecc(nfc, false);
304
305 if (chip->ecc.strength != FMC2_ECC_HAM) {
306 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN,
307 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
308
309 stm32_fmc2_nfc_clear_bch_irq(nfc);
310 }
311
312 stm32_fmc2_nfc_set_ecc(nfc, true);
313 }
314
315 /*
316 * ECC Hamming calculation
317 * ECC is 3 bytes for 512 bytes of data (supports error correction up to
318 * max of 1-bit)
319 */
stm32_fmc2_nfc_ham_calculate(struct mtd_info * mtd,const u8 * data,u8 * ecc)320 static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
321 u8 *ecc)
322 {
323 struct nand_chip *chip = mtd_to_nand(mtd);
324 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
325 u32 heccr, sr;
326 int ret;
327
328 ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
329 sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
330 if (ret < 0) {
331 log_err("Ham timeout\n");
332 return ret;
333 }
334
335 heccr = readl(nfc->io_base + FMC2_HECCR);
336
337 ecc[0] = heccr;
338 ecc[1] = heccr >> 8;
339 ecc[2] = heccr >> 16;
340
341 stm32_fmc2_nfc_set_ecc(nfc, false);
342
343 return 0;
344 }
345
stm32_fmc2_nfc_ham_correct(struct mtd_info * mtd,u8 * dat,u8 * read_ecc,u8 * calc_ecc)346 static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
347 u8 *read_ecc, u8 *calc_ecc)
348 {
349 u8 bit_position = 0, b0, b1, b2;
350 u32 byte_addr = 0, b;
351 u32 i, shifting = 1;
352
353 /* Indicate which bit and byte is faulty (if any) */
354 b0 = read_ecc[0] ^ calc_ecc[0];
355 b1 = read_ecc[1] ^ calc_ecc[1];
356 b2 = read_ecc[2] ^ calc_ecc[2];
357 b = b0 | (b1 << 8) | (b2 << 16);
358
359 /* No errors */
360 if (likely(!b))
361 return 0;
362
363 /* Calculate bit position */
364 for (i = 0; i < 3; i++) {
365 switch (b % 4) {
366 case 2:
367 bit_position += shifting;
368 case 1:
369 break;
370 default:
371 return -EBADMSG;
372 }
373 shifting <<= 1;
374 b >>= 2;
375 }
376
377 /* Calculate byte position */
378 shifting = 1;
379 for (i = 0; i < 9; i++) {
380 switch (b % 4) {
381 case 2:
382 byte_addr += shifting;
383 case 1:
384 break;
385 default:
386 return -EBADMSG;
387 }
388 shifting <<= 1;
389 b >>= 2;
390 }
391
392 /* Flip the bit */
393 dat[byte_addr] ^= (1 << bit_position);
394
395 return 1;
396 }
397
398 /*
399 * ECC BCH calculation and correction
400 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
401 * max of 4-bit/8-bit)
402 */
403
stm32_fmc2_nfc_bch_calculate(struct mtd_info * mtd,const u8 * data,u8 * ecc)404 static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
405 u8 *ecc)
406 {
407 struct nand_chip *chip = mtd_to_nand(mtd);
408 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
409 u32 bchpbr, bchisr;
410 int ret;
411
412 /* Wait until the BCH code is ready */
413 ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
414 bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
415 if (ret < 0) {
416 log_err("Bch timeout\n");
417 return ret;
418 }
419
420 /* Read parity bits */
421 bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
422 ecc[0] = bchpbr;
423 ecc[1] = bchpbr >> 8;
424 ecc[2] = bchpbr >> 16;
425 ecc[3] = bchpbr >> 24;
426
427 bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
428 ecc[4] = bchpbr;
429 ecc[5] = bchpbr >> 8;
430 ecc[6] = bchpbr >> 16;
431
432 if (chip->ecc.strength == FMC2_ECC_BCH8) {
433 ecc[7] = bchpbr >> 24;
434
435 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
436 ecc[8] = bchpbr;
437 ecc[9] = bchpbr >> 8;
438 ecc[10] = bchpbr >> 16;
439 ecc[11] = bchpbr >> 24;
440
441 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
442 ecc[12] = bchpbr;
443 }
444
445 stm32_fmc2_nfc_set_ecc(nfc, false);
446
447 return 0;
448 }
449
stm32_fmc2_nfc_bch_correct(struct mtd_info * mtd,u8 * dat,u8 * read_ecc,u8 * calc_ecc)450 static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
451 u8 *read_ecc, u8 *calc_ecc)
452 {
453 struct nand_chip *chip = mtd_to_nand(mtd);
454 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
455 u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
456 u16 pos[8];
457 int i, ret, den, eccsize = chip->ecc.size;
458 unsigned int nb_errs = 0;
459
460 /* Wait until the decoding error is ready */
461 ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
462 bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
463 if (ret < 0) {
464 log_err("Bch timeout\n");
465 return ret;
466 }
467
468 bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
469 bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
470 bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
471 bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
472 bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
473
474 stm32_fmc2_nfc_set_ecc(nfc, false);
475
476 /* No errors found */
477 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
478 return 0;
479
480 /* Too many errors detected */
481 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
482 return -EBADMSG;
483
484 pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
485 pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
486 pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
487 pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
488 pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
489 pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
490 pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
491 pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
492
493 den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
494 for (i = 0; i < den; i++) {
495 if (pos[i] < eccsize * 8) {
496 __change_bit(pos[i], (unsigned long *)dat);
497 nb_errs++;
498 }
499 }
500
501 return nb_errs;
502 }
503
stm32_fmc2_nfc_read_page(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)504 static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
505 struct nand_chip *chip, u8 *buf,
506 int oob_required, int page)
507 {
508 int i, s, stat, eccsize = chip->ecc.size;
509 int eccbytes = chip->ecc.bytes;
510 int eccsteps = chip->ecc.steps;
511 int eccstrength = chip->ecc.strength;
512 u8 *p = buf;
513 u8 *ecc_calc = chip->buffers->ecccalc;
514 u8 *ecc_code = chip->buffers->ecccode;
515 unsigned int max_bitflips = 0;
516
517 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
518 s++, i += eccbytes, p += eccsize) {
519 chip->ecc.hwctl(mtd, NAND_ECC_READ);
520
521 /* Read the nand page sector (512 bytes) */
522 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
523 chip->read_buf(mtd, p, eccsize);
524
525 /* Read the corresponding ECC bytes */
526 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
527 chip->read_buf(mtd, ecc_code, eccbytes);
528
529 /* Correct the data */
530 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
531 if (stat == -EBADMSG)
532 /* Check for empty pages with bitflips */
533 stat = nand_check_erased_ecc_chunk(p, eccsize,
534 ecc_code, eccbytes,
535 NULL, 0,
536 eccstrength);
537
538 if (stat < 0) {
539 mtd->ecc_stats.failed++;
540 } else {
541 mtd->ecc_stats.corrected += stat;
542 max_bitflips = max_t(unsigned int, max_bitflips, stat);
543 }
544 }
545
546 /* Read oob */
547 if (oob_required) {
548 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
549 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
550 }
551
552 return max_bitflips;
553 }
554
stm32_fmc2_nfc_init(struct stm32_fmc2_nfc * nfc,bool has_parent)555 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent)
556 {
557 u32 pcr = readl(nfc->io_base + FMC2_PCR);
558
559 /* Set CS used to undefined */
560 nfc->cs_sel = -1;
561
562 /* Enable wait feature and nand flash memory bank */
563 pcr |= FMC2_PCR_PWAITEN;
564 pcr |= FMC2_PCR_PBKEN;
565
566 /* Set buswidth to 8 bits mode for identification */
567 pcr &= ~FMC2_PCR_PWID;
568
569 /* ECC logic is disabled */
570 pcr &= ~FMC2_PCR_ECCEN;
571
572 /* Default mode */
573 pcr &= ~FMC2_PCR_ECCALG;
574 pcr &= ~FMC2_PCR_BCHECC;
575 pcr &= ~FMC2_PCR_WEN;
576
577 /* Set default ECC sector size */
578 pcr &= ~FMC2_PCR_ECCSS;
579 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
580
581 /* Set default tclr/tar timings */
582 pcr &= ~FMC2_PCR_TCLR;
583 pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
584 pcr &= ~FMC2_PCR_TAR;
585 pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
586
587 /* Enable FMC2 controller */
588 if (!has_parent)
589 setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
590
591 writel(pcr, nfc->io_base + FMC2_PCR);
592 writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
593 writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
594 }
595
stm32_fmc2_nfc_calc_timings(struct nand_chip * chip,const struct nand_sdr_timings * sdrt)596 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
597 const struct nand_sdr_timings *sdrt)
598 {
599 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
600 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
601 struct stm32_fmc2_timings *tims = &nand->timings;
602 unsigned long hclk = clk_get_rate(&nfc->clk);
603 unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
604 unsigned long timing, tar, tclr, thiz, twait;
605 unsigned long tset_mem, tset_att, thold_mem, thold_att;
606
607 tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
608 timing = DIV_ROUND_UP(tar, hclkp) - 1;
609 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
610
611 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
612 timing = DIV_ROUND_UP(tclr, hclkp) - 1;
613 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
614
615 tims->thiz = FMC2_THIZ;
616 thiz = (tims->thiz + 1) * hclkp;
617
618 /*
619 * tWAIT > tRP
620 * tWAIT > tWP
621 * tWAIT > tREA + tIO
622 */
623 twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
624 twait = max_t(unsigned long, twait, sdrt->tWP_min);
625 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
626 timing = DIV_ROUND_UP(twait, hclkp);
627 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
628
629 /*
630 * tSETUP_MEM > tCS - tWAIT
631 * tSETUP_MEM > tALS - tWAIT
632 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
633 */
634 tset_mem = hclkp;
635 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
636 tset_mem = sdrt->tCS_min - twait;
637 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
638 tset_mem = sdrt->tALS_min - twait;
639 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
640 (tset_mem < sdrt->tDS_min - (twait - thiz)))
641 tset_mem = sdrt->tDS_min - (twait - thiz);
642 timing = DIV_ROUND_UP(tset_mem, hclkp);
643 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
644
645 /*
646 * tHOLD_MEM > tCH
647 * tHOLD_MEM > tREH - tSETUP_MEM
648 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
649 */
650 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
651 if (sdrt->tREH_min > tset_mem &&
652 (thold_mem < sdrt->tREH_min - tset_mem))
653 thold_mem = sdrt->tREH_min - tset_mem;
654 if ((sdrt->tRC_min > tset_mem + twait) &&
655 (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
656 thold_mem = sdrt->tRC_min - (tset_mem + twait);
657 if ((sdrt->tWC_min > tset_mem + twait) &&
658 (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
659 thold_mem = sdrt->tWC_min - (tset_mem + twait);
660 timing = DIV_ROUND_UP(thold_mem, hclkp);
661 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
662
663 /*
664 * tSETUP_ATT > tCS - tWAIT
665 * tSETUP_ATT > tCLS - tWAIT
666 * tSETUP_ATT > tALS - tWAIT
667 * tSETUP_ATT > tRHW - tHOLD_MEM
668 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
669 */
670 tset_att = hclkp;
671 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
672 tset_att = sdrt->tCS_min - twait;
673 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
674 tset_att = sdrt->tCLS_min - twait;
675 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
676 tset_att = sdrt->tALS_min - twait;
677 if (sdrt->tRHW_min > thold_mem &&
678 (tset_att < sdrt->tRHW_min - thold_mem))
679 tset_att = sdrt->tRHW_min - thold_mem;
680 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
681 (tset_att < sdrt->tDS_min - (twait - thiz)))
682 tset_att = sdrt->tDS_min - (twait - thiz);
683 timing = DIV_ROUND_UP(tset_att, hclkp);
684 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
685
686 /*
687 * tHOLD_ATT > tALH
688 * tHOLD_ATT > tCH
689 * tHOLD_ATT > tCLH
690 * tHOLD_ATT > tCOH
691 * tHOLD_ATT > tDH
692 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
693 * tHOLD_ATT > tADL - tSETUP_MEM
694 * tHOLD_ATT > tWH - tSETUP_MEM
695 * tHOLD_ATT > tWHR - tSETUP_MEM
696 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
697 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
698 */
699 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
700 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
701 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
702 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
703 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
704 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
705 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
706 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
707 if (sdrt->tADL_min > tset_mem &&
708 (thold_att < sdrt->tADL_min - tset_mem))
709 thold_att = sdrt->tADL_min - tset_mem;
710 if (sdrt->tWH_min > tset_mem &&
711 (thold_att < sdrt->tWH_min - tset_mem))
712 thold_att = sdrt->tWH_min - tset_mem;
713 if (sdrt->tWHR_min > tset_mem &&
714 (thold_att < sdrt->tWHR_min - tset_mem))
715 thold_att = sdrt->tWHR_min - tset_mem;
716 if ((sdrt->tRC_min > tset_att + twait) &&
717 (thold_att < sdrt->tRC_min - (tset_att + twait)))
718 thold_att = sdrt->tRC_min - (tset_att + twait);
719 if ((sdrt->tWC_min > tset_att + twait) &&
720 (thold_att < sdrt->tWC_min - (tset_att + twait)))
721 thold_att = sdrt->tWC_min - (tset_att + twait);
722 timing = DIV_ROUND_UP(thold_att, hclkp);
723 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
724 }
725
stm32_fmc2_nfc_setup_interface(struct mtd_info * mtd,int chipnr,const struct nand_data_interface * cf)726 static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
727 const struct nand_data_interface *cf)
728 {
729 struct nand_chip *chip = mtd_to_nand(mtd);
730 const struct nand_sdr_timings *sdrt;
731
732 sdrt = nand_get_sdr_timings(cf);
733 if (IS_ERR(sdrt))
734 return PTR_ERR(sdrt);
735
736 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
737 return 0;
738
739 stm32_fmc2_nfc_calc_timings(chip, sdrt);
740 stm32_fmc2_nfc_timings_init(chip);
741
742 return 0;
743 }
744
stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip * chip)745 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
746 {
747 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
748
749 /*
750 * Specific callbacks to read/write a page depending on
751 * the algo used (Hamming, BCH).
752 */
753 if (chip->ecc.strength == FMC2_ECC_HAM) {
754 /* Hamming is used */
755 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
756 chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
757 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
758 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
759 return;
760 }
761
762 /* BCH is used */
763 chip->ecc.read_page = stm32_fmc2_nfc_read_page;
764 chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
765 chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
766
767 if (chip->ecc.strength == FMC2_ECC_BCH8)
768 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
769 else
770 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
771 }
772
stm32_fmc2_nfc_calc_ecc_bytes(int step_size,int strength)773 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
774 {
775 /* Hamming */
776 if (strength == FMC2_ECC_HAM)
777 return 4;
778
779 /* BCH8 */
780 if (strength == FMC2_ECC_BCH8)
781 return 14;
782
783 /* BCH4 */
784 return 8;
785 }
786
787 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
788 FMC2_ECC_STEP_SIZE,
789 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
790
stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc * nfc,ofnode node)791 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
792 {
793 struct stm32_fmc2_nand *nand = &nfc->nand;
794 u32 cs[FMC2_MAX_CE];
795 int ret, i;
796
797 if (!ofnode_get_property(node, "reg", &nand->ncs))
798 return -EINVAL;
799
800 nand->ncs /= sizeof(u32);
801 if (!nand->ncs) {
802 log_err("Invalid reg property size\n");
803 return -EINVAL;
804 }
805
806 ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
807 if (ret < 0) {
808 log_err("Could not retrieve reg property\n");
809 return -EINVAL;
810 }
811
812 for (i = 0; i < nand->ncs; i++) {
813 if (cs[i] >= FMC2_MAX_CE) {
814 log_err("Invalid reg value: %d\n", nand->cs_used[i]);
815 return -EINVAL;
816 }
817
818 if (nfc->cs_assigned & BIT(cs[i])) {
819 log_err("Cs already assigned: %d\n", nand->cs_used[i]);
820 return -EINVAL;
821 }
822
823 nfc->cs_assigned |= BIT(cs[i]);
824 nand->cs_used[i] = cs[i];
825 }
826
827 nand->chip.flash_node = node;
828
829 return 0;
830 }
831
stm32_fmc2_nfc_parse_dt(struct udevice * dev,struct stm32_fmc2_nfc * nfc)832 static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
833 struct stm32_fmc2_nfc *nfc)
834 {
835 ofnode child;
836 int ret, nchips = 0;
837
838 dev_for_each_subnode(child, dev)
839 nchips++;
840
841 if (!nchips) {
842 log_err("NAND chip not defined\n");
843 return -EINVAL;
844 }
845
846 if (nchips > 1) {
847 log_err("Too many NAND chips defined\n");
848 return -EINVAL;
849 }
850
851 dev_for_each_subnode(child, dev) {
852 ret = stm32_fmc2_nfc_parse_child(nfc, child);
853 if (ret)
854 return ret;
855 }
856
857 return 0;
858 }
859
stm32_fmc2_nfc_get_cdev(struct udevice * dev)860 static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev)
861 {
862 struct udevice *pdev = dev_get_parent(dev);
863 struct udevice *cdev = NULL;
864 bool ebi_found = false;
865
866 if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev),
867 "st,stm32mp1-fmc2-ebi"))
868 ebi_found = true;
869
870 if (ofnode_device_is_compatible(dev_ofnode(dev),
871 "st,stm32mp1-fmc2-nfc")) {
872 if (ebi_found)
873 cdev = pdev;
874
875 return cdev;
876 }
877
878 if (!ebi_found)
879 cdev = dev;
880
881 return cdev;
882 }
883
stm32_fmc2_nfc_probe(struct udevice * dev)884 static int stm32_fmc2_nfc_probe(struct udevice *dev)
885 {
886 struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
887 struct stm32_fmc2_nand *nand = &nfc->nand;
888 struct nand_chip *chip = &nand->chip;
889 struct mtd_info *mtd = &chip->mtd;
890 struct nand_ecclayout *ecclayout;
891 struct udevice *cdev;
892 struct reset_ctl reset;
893 int oob_index, chip_cs, mem_region, ret;
894 unsigned int i;
895 int start_region = 0;
896 fdt_addr_t addr;
897
898 spin_lock_init(&nfc->controller.lock);
899 init_waitqueue_head(&nfc->controller.wq);
900
901 cdev = stm32_fmc2_nfc_get_cdev(dev);
902 if (!cdev)
903 return -EINVAL;
904
905 ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
906 if (ret)
907 return ret;
908
909 nfc->io_base = dev_read_addr(cdev);
910 if (nfc->io_base == FDT_ADDR_T_NONE)
911 return -EINVAL;
912
913 if (dev == cdev)
914 start_region = 1;
915
916 for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
917 chip_cs++, mem_region += 3) {
918 if (!(nfc->cs_assigned & BIT(chip_cs)))
919 continue;
920
921 addr = dev_read_addr_index(dev, mem_region);
922 if (addr == FDT_ADDR_T_NONE) {
923 dev_err(dev, "Resource data_base not found for cs%d", chip_cs);
924 return ret;
925 }
926 nfc->data_base[chip_cs] = addr;
927
928 addr = dev_read_addr_index(dev, mem_region + 1);
929 if (addr == FDT_ADDR_T_NONE) {
930 dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs);
931 return ret;
932 }
933 nfc->cmd_base[chip_cs] = addr;
934
935 addr = dev_read_addr_index(dev, mem_region + 2);
936 if (addr == FDT_ADDR_T_NONE) {
937 dev_err(dev, "Resource addr_base not found for cs%d", chip_cs);
938 return ret;
939 }
940 nfc->addr_base[chip_cs] = addr;
941 }
942
943 /* Enable the clock */
944 ret = clk_get_by_index(cdev, 0, &nfc->clk);
945 if (ret)
946 return ret;
947
948 ret = clk_enable(&nfc->clk);
949 if (ret)
950 return ret;
951
952 /* Reset */
953 ret = reset_get_by_index(dev, 0, &reset);
954 if (!ret) {
955 reset_assert(&reset);
956 udelay(2);
957 reset_deassert(&reset);
958 }
959
960 stm32_fmc2_nfc_init(nfc, dev != cdev);
961
962 chip->controller = &nfc->base;
963 chip->select_chip = stm32_fmc2_nfc_select_chip;
964 chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
965 chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
966 chip->chip_delay = FMC2_RB_DELAY_US;
967 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
968 NAND_USE_BOUNCE_BUFFER;
969
970 /* Default ECC settings */
971 chip->ecc.mode = NAND_ECC_HW;
972 chip->ecc.size = FMC2_ECC_STEP_SIZE;
973 chip->ecc.strength = FMC2_ECC_BCH8;
974
975 ret = nand_scan_ident(mtd, nand->ncs, NULL);
976 if (ret)
977 return ret;
978
979 /*
980 * Only NAND_ECC_HW mode is actually supported
981 * Hamming => ecc.strength = 1
982 * BCH4 => ecc.strength = 4
983 * BCH8 => ecc.strength = 8
984 * ECC sector size = 512
985 */
986 if (chip->ecc.mode != NAND_ECC_HW) {
987 dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n");
988 return -EINVAL;
989 }
990
991 ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
992 mtd->oobsize - FMC2_BBM_LEN);
993 if (ret) {
994 dev_err(dev, "No valid ECC settings set\n");
995 return ret;
996 }
997
998 if (chip->bbt_options & NAND_BBT_USE_FLASH)
999 chip->bbt_options |= NAND_BBT_NO_OOB;
1000
1001 stm32_fmc2_nfc_nand_callbacks_setup(chip);
1002
1003 /* Define ECC layout */
1004 ecclayout = &nfc->ecclayout;
1005 ecclayout->eccbytes = chip->ecc.bytes *
1006 (mtd->writesize / chip->ecc.size);
1007 oob_index = FMC2_BBM_LEN;
1008 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1009 ecclayout->eccpos[i] = oob_index;
1010 ecclayout->oobfree->offset = oob_index;
1011 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1012 chip->ecc.layout = ecclayout;
1013
1014 if (chip->options & NAND_BUSWIDTH_16)
1015 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1016
1017 ret = nand_scan_tail(mtd);
1018 if (ret)
1019 return ret;
1020
1021 return nand_register(0, mtd);
1022 }
1023
1024 static const struct udevice_id stm32_fmc2_nfc_match[] = {
1025 { .compatible = "st,stm32mp15-fmc2" },
1026 { .compatible = "st,stm32mp1-fmc2-nfc" },
1027 { /* Sentinel */ }
1028 };
1029
1030 U_BOOT_DRIVER(stm32_fmc2_nfc) = {
1031 .name = "stm32_fmc2_nfc",
1032 .id = UCLASS_MTD,
1033 .of_match = stm32_fmc2_nfc_match,
1034 .probe = stm32_fmc2_nfc_probe,
1035 .priv_auto = sizeof(struct stm32_fmc2_nfc),
1036 };
1037
board_nand_init(void)1038 void board_nand_init(void)
1039 {
1040 struct udevice *dev;
1041 int ret;
1042
1043 ret = uclass_get_device_by_driver(UCLASS_MTD,
1044 DM_DRIVER_GET(stm32_fmc2_nfc),
1045 &dev);
1046 if (ret && ret != -ENODEV)
1047 log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
1048 ret);
1049 }
1050