1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
6 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11 */
12
13 #include <cpu_func.h>
14 #include <log.h>
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <common.h>
21 #include <clk.h>
22 #include <dm.h>
23 #include <fdt_support.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <malloc.h>
29 #include <miiphy.h>
30 #include <net.h>
31 #include <reset.h>
32 #include <dt-bindings/pinctrl/sun4i-a10.h>
33 #include <wait_bit.h>
34
35 #define MDIO_CMD_MII_BUSY BIT(0)
36 #define MDIO_CMD_MII_WRITE BIT(1)
37
38 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
39 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
40 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
41 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
42 #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
43 #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
44 #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
45 #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
46 #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
47
48 #define CONFIG_TX_DESCR_NUM 32
49 #define CONFIG_RX_DESCR_NUM 32
50 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
51
52 /*
53 * The datasheet says that each descriptor can transfers up to 4096 bytes
54 * But later, the register documentation reduces that value to 2048,
55 * using 2048 cause strange behaviours and even BSP driver use 2047
56 */
57 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
58
59 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
60 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
61
62 #define H3_EPHY_DEFAULT_VALUE 0x58000
63 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
64 #define H3_EPHY_ADDR_SHIFT 20
65 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
66 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
67 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
68 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
69
70 #define SC_RMII_EN BIT(13)
71 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
72 #define SC_ETCS_MASK GENMASK(1, 0)
73 #define SC_ETCS_EXT_GMII 0x1
74 #define SC_ETCS_INT_GMII 0x2
75 #define SC_ETXDC_MASK GENMASK(12, 10)
76 #define SC_ETXDC_OFFSET 10
77 #define SC_ERXDC_MASK GENMASK(9, 5)
78 #define SC_ERXDC_OFFSET 5
79
80 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
81
82 #define AHB_GATE_OFFSET_EPHY 0
83
84 /* IO mux settings */
85 #define SUN8I_IOMUX_H3 2
86 #define SUN8I_IOMUX_R40 5
87 #define SUN8I_IOMUX_H6 5
88 #define SUN8I_IOMUX_H616 2
89 #define SUN8I_IOMUX 4
90
91 /* H3/A64 EMAC Register's offset */
92 #define EMAC_CTL0 0x00
93 #define EMAC_CTL0_FULL_DUPLEX BIT(0)
94 #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
95 #define EMAC_CTL0_SPEED_10 (0x2 << 2)
96 #define EMAC_CTL0_SPEED_100 (0x3 << 2)
97 #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
98 #define EMAC_CTL1 0x04
99 #define EMAC_CTL1_SOFT_RST BIT(0)
100 #define EMAC_CTL1_BURST_LEN_SHIFT 24
101 #define EMAC_INT_STA 0x08
102 #define EMAC_INT_EN 0x0c
103 #define EMAC_TX_CTL0 0x10
104 #define EMAC_TX_CTL0_TX_EN BIT(31)
105 #define EMAC_TX_CTL1 0x14
106 #define EMAC_TX_CTL1_TX_MD BIT(1)
107 #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
108 #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
109 #define EMAC_TX_FLOW_CTL 0x1c
110 #define EMAC_TX_DMA_DESC 0x20
111 #define EMAC_RX_CTL0 0x24
112 #define EMAC_RX_CTL0_RX_EN BIT(31)
113 #define EMAC_RX_CTL1 0x28
114 #define EMAC_RX_CTL1_RX_MD BIT(1)
115 #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
116 #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
117 #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
118 #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
119 #define EMAC_RX_DMA_DESC 0x34
120 #define EMAC_MII_CMD 0x48
121 #define EMAC_MII_DATA 0x4c
122 #define EMAC_ADDR0_HIGH 0x50
123 #define EMAC_ADDR0_LOW 0x54
124 #define EMAC_TX_DMA_STA 0xb0
125 #define EMAC_TX_CUR_DESC 0xb4
126 #define EMAC_TX_CUR_BUF 0xb8
127 #define EMAC_RX_DMA_STA 0xc0
128 #define EMAC_RX_CUR_DESC 0xc4
129
130 #define EMAC_DESC_OWN_DMA BIT(31)
131 #define EMAC_DESC_LAST_DESC BIT(30)
132 #define EMAC_DESC_FIRST_DESC BIT(29)
133 #define EMAC_DESC_CHAIN_SECOND BIT(24)
134
135 #define EMAC_DESC_RX_ERROR_MASK 0x400068db
136
137 DECLARE_GLOBAL_DATA_PTR;
138
139 enum emac_variant {
140 A83T_EMAC = 1,
141 H3_EMAC,
142 A64_EMAC,
143 R40_GMAC,
144 H6_EMAC,
145 };
146
147 struct emac_dma_desc {
148 u32 status;
149 u32 ctl_size;
150 u32 buf_addr;
151 u32 next;
152 } __aligned(ARCH_DMA_MINALIGN);
153
154 struct emac_eth_dev {
155 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
156 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
157 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
158 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
159
160 u32 interface;
161 u32 phyaddr;
162 u32 link;
163 u32 speed;
164 u32 duplex;
165 u32 phy_configured;
166 u32 tx_currdescnum;
167 u32 rx_currdescnum;
168 u32 addr;
169 u32 tx_slot;
170 bool use_internal_phy;
171
172 enum emac_variant variant;
173 void *mac_reg;
174 phys_addr_t sysctl_reg;
175 struct phy_device *phydev;
176 struct mii_dev *bus;
177 struct clk tx_clk;
178 struct clk ephy_clk;
179 struct reset_ctl tx_rst;
180 struct reset_ctl ephy_rst;
181 #if CONFIG_IS_ENABLED(DM_GPIO)
182 struct gpio_desc reset_gpio;
183 #endif
184 };
185
186
187 struct sun8i_eth_pdata {
188 struct eth_pdata eth_pdata;
189 u32 reset_delays[3];
190 int tx_delay_ps;
191 int rx_delay_ps;
192 };
193
194
sun8i_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)195 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
196 {
197 struct udevice *dev = bus->priv;
198 struct emac_eth_dev *priv = dev_get_priv(dev);
199 u32 mii_cmd;
200 int ret;
201
202 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
203 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
204 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
205 MDIO_CMD_MII_PHY_ADDR_MASK;
206
207 /*
208 * The EMAC clock is either 200 or 300 MHz, so we need a divider
209 * of 128 to get the MDIO frequency below the required 2.5 MHz.
210 */
211 if (!priv->use_internal_phy)
212 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
213 MDIO_CMD_MII_CLK_CSR_SHIFT;
214
215 mii_cmd |= MDIO_CMD_MII_BUSY;
216
217 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
218
219 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
220 MDIO_CMD_MII_BUSY, false,
221 CONFIG_MDIO_TIMEOUT, true);
222 if (ret < 0)
223 return ret;
224
225 return readl(priv->mac_reg + EMAC_MII_DATA);
226 }
227
sun8i_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)228 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
229 u16 val)
230 {
231 struct udevice *dev = bus->priv;
232 struct emac_eth_dev *priv = dev_get_priv(dev);
233 u32 mii_cmd;
234
235 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
236 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
237 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
238 MDIO_CMD_MII_PHY_ADDR_MASK;
239
240 /*
241 * The EMAC clock is either 200 or 300 MHz, so we need a divider
242 * of 128 to get the MDIO frequency below the required 2.5 MHz.
243 */
244 if (!priv->use_internal_phy)
245 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
246 MDIO_CMD_MII_CLK_CSR_SHIFT;
247
248 mii_cmd |= MDIO_CMD_MII_WRITE;
249 mii_cmd |= MDIO_CMD_MII_BUSY;
250
251 writel(val, priv->mac_reg + EMAC_MII_DATA);
252 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
253
254 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
255 MDIO_CMD_MII_BUSY, false,
256 CONFIG_MDIO_TIMEOUT, true);
257 }
258
sun8i_eth_write_hwaddr(struct udevice * dev)259 static int sun8i_eth_write_hwaddr(struct udevice *dev)
260 {
261 struct emac_eth_dev *priv = dev_get_priv(dev);
262 struct eth_pdata *pdata = dev_get_plat(dev);
263 uchar *mac_id = pdata->enetaddr;
264 u32 macid_lo, macid_hi;
265
266 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
267 (mac_id[3] << 24);
268 macid_hi = mac_id[4] + (mac_id[5] << 8);
269
270 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
271 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
272
273 return 0;
274 }
275
sun8i_adjust_link(struct emac_eth_dev * priv,struct phy_device * phydev)276 static void sun8i_adjust_link(struct emac_eth_dev *priv,
277 struct phy_device *phydev)
278 {
279 u32 v;
280
281 v = readl(priv->mac_reg + EMAC_CTL0);
282
283 if (phydev->duplex)
284 v |= EMAC_CTL0_FULL_DUPLEX;
285 else
286 v &= ~EMAC_CTL0_FULL_DUPLEX;
287
288 v &= ~EMAC_CTL0_SPEED_MASK;
289
290 switch (phydev->speed) {
291 case 1000:
292 v |= EMAC_CTL0_SPEED_1000;
293 break;
294 case 100:
295 v |= EMAC_CTL0_SPEED_100;
296 break;
297 case 10:
298 v |= EMAC_CTL0_SPEED_10;
299 break;
300 }
301 writel(v, priv->mac_reg + EMAC_CTL0);
302 }
303
sun8i_emac_set_syscon_ephy(struct emac_eth_dev * priv,u32 reg)304 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
305 {
306 if (priv->use_internal_phy) {
307 /* H3 based SoC's that has an Internal 100MBit PHY
308 * needs to be configured and powered up before use
309 */
310 reg &= ~H3_EPHY_DEFAULT_MASK;
311 reg |= H3_EPHY_DEFAULT_VALUE;
312 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
313 reg &= ~H3_EPHY_SHUTDOWN;
314 return reg | H3_EPHY_SELECT;
315 }
316
317 /* This is to select External Gigabit PHY on those boards with
318 * an internal PHY. Does not hurt on other SoCs. Linux does
319 * it as well.
320 */
321 return reg & ~H3_EPHY_SELECT;
322 }
323
sun8i_emac_set_syscon(struct sun8i_eth_pdata * pdata,struct emac_eth_dev * priv)324 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
325 struct emac_eth_dev *priv)
326 {
327 u32 reg;
328
329 if (priv->variant == R40_GMAC) {
330 /* Select RGMII for R40 */
331 reg = readl(priv->sysctl_reg + 0x164);
332 reg |= SC_ETCS_INT_GMII |
333 SC_EPIT |
334 (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
335
336 writel(reg, priv->sysctl_reg + 0x164);
337 return 0;
338 }
339
340 reg = readl(priv->sysctl_reg + 0x30);
341
342 reg = sun8i_emac_set_syscon_ephy(priv, reg);
343
344 reg &= ~(SC_ETCS_MASK | SC_EPIT);
345 if (priv->variant == H3_EMAC ||
346 priv->variant == A64_EMAC ||
347 priv->variant == H6_EMAC)
348 reg &= ~SC_RMII_EN;
349
350 switch (priv->interface) {
351 case PHY_INTERFACE_MODE_MII:
352 /* default */
353 break;
354 case PHY_INTERFACE_MODE_RGMII:
355 case PHY_INTERFACE_MODE_RGMII_ID:
356 case PHY_INTERFACE_MODE_RGMII_RXID:
357 case PHY_INTERFACE_MODE_RGMII_TXID:
358 reg |= SC_EPIT | SC_ETCS_INT_GMII;
359 break;
360 case PHY_INTERFACE_MODE_RMII:
361 if (priv->variant == H3_EMAC ||
362 priv->variant == A64_EMAC ||
363 priv->variant == H6_EMAC) {
364 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
365 break;
366 }
367 /* RMII not supported on A83T */
368 default:
369 debug("%s: Invalid PHY interface\n", __func__);
370 return -EINVAL;
371 }
372
373 if (pdata->tx_delay_ps)
374 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
375 & SC_ETXDC_MASK;
376
377 if (pdata->rx_delay_ps)
378 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
379 & SC_ERXDC_MASK;
380
381 writel(reg, priv->sysctl_reg + 0x30);
382
383 return 0;
384 }
385
sun8i_phy_init(struct emac_eth_dev * priv,void * dev)386 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
387 {
388 struct phy_device *phydev;
389
390 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
391 if (!phydev)
392 return -ENODEV;
393
394 phy_connect_dev(phydev, dev);
395
396 priv->phydev = phydev;
397 phy_config(priv->phydev);
398
399 return 0;
400 }
401
402 #define cache_clean_descriptor(desc) \
403 flush_dcache_range((uintptr_t)(desc), \
404 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
405
406 #define cache_inv_descriptor(desc) \
407 invalidate_dcache_range((uintptr_t)(desc), \
408 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
409
rx_descs_init(struct emac_eth_dev * priv)410 static void rx_descs_init(struct emac_eth_dev *priv)
411 {
412 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
413 char *rxbuffs = &priv->rxbuffer[0];
414 struct emac_dma_desc *desc_p;
415 int i;
416
417 /*
418 * Make sure we don't have dirty cache lines around, which could
419 * be cleaned to DRAM *after* the MAC has already written data to it.
420 */
421 invalidate_dcache_range((uintptr_t)desc_table_p,
422 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
423 invalidate_dcache_range((uintptr_t)rxbuffs,
424 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
425
426 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
427 desc_p = &desc_table_p[i];
428 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
429 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
430 desc_p->ctl_size = CONFIG_ETH_RXSIZE;
431 desc_p->status = EMAC_DESC_OWN_DMA;
432 }
433
434 /* Correcting the last pointer of the chain */
435 desc_p->next = (uintptr_t)&desc_table_p[0];
436
437 flush_dcache_range((uintptr_t)priv->rx_chain,
438 (uintptr_t)priv->rx_chain +
439 sizeof(priv->rx_chain));
440
441 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
442 priv->rx_currdescnum = 0;
443 }
444
tx_descs_init(struct emac_eth_dev * priv)445 static void tx_descs_init(struct emac_eth_dev *priv)
446 {
447 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
448 char *txbuffs = &priv->txbuffer[0];
449 struct emac_dma_desc *desc_p;
450 int i;
451
452 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
453 desc_p = &desc_table_p[i];
454 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
455 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
456 desc_p->ctl_size = 0;
457 desc_p->status = 0;
458 }
459
460 /* Correcting the last pointer of the chain */
461 desc_p->next = (uintptr_t)&desc_table_p[0];
462
463 /* Flush the first TX buffer descriptor we will tell the MAC about. */
464 cache_clean_descriptor(desc_table_p);
465
466 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
467 priv->tx_currdescnum = 0;
468 }
469
sun8i_emac_eth_start(struct udevice * dev)470 static int sun8i_emac_eth_start(struct udevice *dev)
471 {
472 struct emac_eth_dev *priv = dev_get_priv(dev);
473 int ret;
474
475 /* Soft reset MAC */
476 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
477 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
478 EMAC_CTL1_SOFT_RST, false, 10, true);
479 if (ret) {
480 printf("%s: Timeout\n", __func__);
481 return ret;
482 }
483
484 /* Rewrite mac address after reset */
485 sun8i_eth_write_hwaddr(dev);
486
487 /* transmission starts after the full frame arrived in TX DMA FIFO */
488 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
489
490 /*
491 * RX DMA reads data from RX DMA FIFO to host memory after a
492 * complete frame has been written to RX DMA FIFO
493 */
494 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
495
496 /* DMA burst length */
497 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
498
499 /* Initialize rx/tx descriptors */
500 rx_descs_init(priv);
501 tx_descs_init(priv);
502
503 /* PHY Start Up */
504 ret = phy_startup(priv->phydev);
505 if (ret)
506 return ret;
507
508 sun8i_adjust_link(priv, priv->phydev);
509
510 /* Start RX/TX DMA */
511 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
512 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
513 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
514
515 /* Enable RX/TX */
516 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
517 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
518
519 return 0;
520 }
521
parse_phy_pins(struct udevice * dev)522 static int parse_phy_pins(struct udevice *dev)
523 {
524 int offset;
525 const char *pin_name;
526 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
527 u32 iomux;
528
529 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
530 "pinctrl-0");
531 if (offset < 0) {
532 printf("WARNING: emac: cannot find pinctrl-0 node\n");
533 return offset;
534 }
535
536 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
537 "drive-strength", ~0);
538 if (drive != ~0) {
539 if (drive <= 10)
540 drive = SUN4I_PINCTRL_10_MA;
541 else if (drive <= 20)
542 drive = SUN4I_PINCTRL_20_MA;
543 else if (drive <= 30)
544 drive = SUN4I_PINCTRL_30_MA;
545 else
546 drive = SUN4I_PINCTRL_40_MA;
547 }
548
549 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
550 pull = SUN4I_PINCTRL_PULL_UP;
551 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
552 pull = SUN4I_PINCTRL_PULL_DOWN;
553
554 /*
555 * The GPIO pinmux value is an integration choice, so depends on the
556 * SoC, not the EMAC variant.
557 */
558 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
559 iomux = SUN8I_IOMUX_H3;
560 else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
561 iomux = SUN8I_IOMUX_R40;
562 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
563 iomux = SUN8I_IOMUX_H6;
564 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
565 iomux = SUN8I_IOMUX_H616;
566 else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
567 iomux = SUN8I_IOMUX;
568 else if (IS_ENABLED(CONFIG_MACH_SUN50I))
569 iomux = SUN8I_IOMUX;
570 else
571 BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
572
573 for (i = 0; ; i++) {
574 int pin;
575
576 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
577 "pins", i, NULL);
578 if (!pin_name)
579 break;
580
581 pin = sunxi_name_to_gpio(pin_name);
582 if (pin < 0)
583 continue;
584
585 sunxi_gpio_set_cfgpin(pin, iomux);
586
587 if (drive != ~0)
588 sunxi_gpio_set_drv(pin, drive);
589 if (pull != ~0)
590 sunxi_gpio_set_pull(pin, pull);
591 }
592
593 if (!i) {
594 printf("WARNING: emac: cannot find pins property\n");
595 return -2;
596 }
597
598 return 0;
599 }
600
sun8i_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)601 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
602 {
603 struct emac_eth_dev *priv = dev_get_priv(dev);
604 u32 status, desc_num = priv->rx_currdescnum;
605 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
606 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
607 int length;
608
609 /* Invalidate entire buffer descriptor */
610 cache_inv_descriptor(desc_p);
611
612 status = desc_p->status;
613
614 /* Check for DMA own bit */
615 if (status & EMAC_DESC_OWN_DMA)
616 return -EAGAIN;
617
618 length = (status >> 16) & 0x3fff;
619
620 /* make sure we read from DRAM, not our cache */
621 invalidate_dcache_range(data_start,
622 data_start + roundup(length, ARCH_DMA_MINALIGN));
623
624 if (status & EMAC_DESC_RX_ERROR_MASK) {
625 debug("RX: packet error: 0x%x\n",
626 status & EMAC_DESC_RX_ERROR_MASK);
627 return 0;
628 }
629 if (length < 0x40) {
630 debug("RX: Bad Packet (runt)\n");
631 return 0;
632 }
633
634 if (length > CONFIG_ETH_RXSIZE) {
635 debug("RX: Too large packet (%d bytes)\n", length);
636 return 0;
637 }
638
639 *packetp = (uchar *)(ulong)desc_p->buf_addr;
640
641 return length;
642 }
643
sun8i_emac_eth_send(struct udevice * dev,void * packet,int length)644 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
645 {
646 struct emac_eth_dev *priv = dev_get_priv(dev);
647 u32 desc_num = priv->tx_currdescnum;
648 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
649 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
650 uintptr_t data_end = data_start +
651 roundup(length, ARCH_DMA_MINALIGN);
652
653 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
654
655 memcpy((void *)data_start, packet, length);
656
657 /* Flush data to be sent */
658 flush_dcache_range(data_start, data_end);
659
660 /* frame begin and end */
661 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
662 desc_p->status = EMAC_DESC_OWN_DMA;
663
664 /* make sure the MAC reads the actual data from DRAM */
665 cache_clean_descriptor(desc_p);
666
667 /* Move to next Descriptor and wrap around */
668 if (++desc_num >= CONFIG_TX_DESCR_NUM)
669 desc_num = 0;
670 priv->tx_currdescnum = desc_num;
671
672 /* Start the DMA */
673 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
674
675 /*
676 * Since we copied the data above, we return here without waiting
677 * for the packet to be actually send out.
678 */
679
680 return 0;
681 }
682
sun8i_emac_board_setup(struct udevice * dev,struct emac_eth_dev * priv)683 static int sun8i_emac_board_setup(struct udevice *dev,
684 struct emac_eth_dev *priv)
685 {
686 int ret;
687
688 ret = clk_enable(&priv->tx_clk);
689 if (ret) {
690 dev_err(dev, "failed to enable TX clock\n");
691 return ret;
692 }
693
694 if (reset_valid(&priv->tx_rst)) {
695 ret = reset_deassert(&priv->tx_rst);
696 if (ret) {
697 dev_err(dev, "failed to deassert TX reset\n");
698 goto err_tx_clk;
699 }
700 }
701
702 /* Only H3/H5 have clock controls for internal EPHY */
703 if (clk_valid(&priv->ephy_clk)) {
704 ret = clk_enable(&priv->ephy_clk);
705 if (ret) {
706 dev_err(dev, "failed to enable EPHY TX clock\n");
707 return ret;
708 }
709 }
710
711 if (reset_valid(&priv->ephy_rst)) {
712 ret = reset_deassert(&priv->ephy_rst);
713 if (ret) {
714 dev_err(dev, "failed to deassert EPHY TX clock\n");
715 return ret;
716 }
717 }
718
719 return 0;
720
721 err_tx_clk:
722 clk_disable(&priv->tx_clk);
723 return ret;
724 }
725
726 #if CONFIG_IS_ENABLED(DM_GPIO)
sun8i_mdio_reset(struct mii_dev * bus)727 static int sun8i_mdio_reset(struct mii_dev *bus)
728 {
729 struct udevice *dev = bus->priv;
730 struct emac_eth_dev *priv = dev_get_priv(dev);
731 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
732 int ret;
733
734 if (!dm_gpio_is_valid(&priv->reset_gpio))
735 return 0;
736
737 /* reset the phy */
738 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
739 if (ret)
740 return ret;
741
742 udelay(pdata->reset_delays[0]);
743
744 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
745 if (ret)
746 return ret;
747
748 udelay(pdata->reset_delays[1]);
749
750 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
751 if (ret)
752 return ret;
753
754 udelay(pdata->reset_delays[2]);
755
756 return 0;
757 }
758 #endif
759
sun8i_mdio_init(const char * name,struct udevice * priv)760 static int sun8i_mdio_init(const char *name, struct udevice *priv)
761 {
762 struct mii_dev *bus = mdio_alloc();
763
764 if (!bus) {
765 debug("Failed to allocate MDIO bus\n");
766 return -ENOMEM;
767 }
768
769 bus->read = sun8i_mdio_read;
770 bus->write = sun8i_mdio_write;
771 snprintf(bus->name, sizeof(bus->name), name);
772 bus->priv = (void *)priv;
773 #if CONFIG_IS_ENABLED(DM_GPIO)
774 bus->reset = sun8i_mdio_reset;
775 #endif
776
777 return mdio_register(bus);
778 }
779
sun8i_eth_free_pkt(struct udevice * dev,uchar * packet,int length)780 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
781 int length)
782 {
783 struct emac_eth_dev *priv = dev_get_priv(dev);
784 u32 desc_num = priv->rx_currdescnum;
785 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
786
787 /* give the current descriptor back to the MAC */
788 desc_p->status |= EMAC_DESC_OWN_DMA;
789
790 /* Flush Status field of descriptor */
791 cache_clean_descriptor(desc_p);
792
793 /* Move to next desc and wrap-around condition. */
794 if (++desc_num >= CONFIG_RX_DESCR_NUM)
795 desc_num = 0;
796 priv->rx_currdescnum = desc_num;
797
798 return 0;
799 }
800
sun8i_emac_eth_stop(struct udevice * dev)801 static void sun8i_emac_eth_stop(struct udevice *dev)
802 {
803 struct emac_eth_dev *priv = dev_get_priv(dev);
804
805 /* Stop Rx/Tx transmitter */
806 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
807 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
808
809 /* Stop RX/TX DMA */
810 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
811 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
812
813 phy_shutdown(priv->phydev);
814 }
815
sun8i_emac_eth_probe(struct udevice * dev)816 static int sun8i_emac_eth_probe(struct udevice *dev)
817 {
818 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
819 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
820 struct emac_eth_dev *priv = dev_get_priv(dev);
821 int ret;
822
823 priv->mac_reg = (void *)pdata->iobase;
824
825 ret = sun8i_emac_board_setup(dev, priv);
826 if (ret)
827 return ret;
828
829 sun8i_emac_set_syscon(sun8i_pdata, priv);
830
831 sun8i_mdio_init(dev->name, dev);
832 priv->bus = miiphy_get_dev_by_name(dev->name);
833
834 return sun8i_phy_init(priv, dev);
835 }
836
837 static const struct eth_ops sun8i_emac_eth_ops = {
838 .start = sun8i_emac_eth_start,
839 .write_hwaddr = sun8i_eth_write_hwaddr,
840 .send = sun8i_emac_eth_send,
841 .recv = sun8i_emac_eth_recv,
842 .free_pkt = sun8i_eth_free_pkt,
843 .stop = sun8i_emac_eth_stop,
844 };
845
sun8i_handle_internal_phy(struct udevice * dev,struct emac_eth_dev * priv)846 static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
847 {
848 struct ofnode_phandle_args phandle;
849 int ret;
850
851 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
852 NULL, 0, 0, &phandle);
853 if (ret)
854 return ret;
855
856 /* If the PHY node is not a child of the internal MDIO bus, we are
857 * using some external PHY.
858 */
859 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
860 "allwinner,sun8i-h3-mdio-internal"))
861 return 0;
862
863 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
864 if (ret) {
865 dev_err(dev, "failed to get EPHY TX clock\n");
866 return ret;
867 }
868
869 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
870 if (ret) {
871 dev_err(dev, "failed to get EPHY TX reset\n");
872 return ret;
873 }
874
875 priv->use_internal_phy = true;
876
877 return 0;
878 }
879
sun8i_emac_eth_of_to_plat(struct udevice * dev)880 static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
881 {
882 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
883 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
884 struct emac_eth_dev *priv = dev_get_priv(dev);
885 const char *phy_mode;
886 const fdt32_t *reg;
887 int node = dev_of_offset(dev);
888 int offset = 0;
889 #if CONFIG_IS_ENABLED(DM_GPIO)
890 int reset_flags = GPIOD_IS_OUT;
891 #endif
892 int ret;
893
894 pdata->iobase = dev_read_addr(dev);
895 if (pdata->iobase == FDT_ADDR_T_NONE) {
896 debug("%s: Cannot find MAC base address\n", __func__);
897 return -EINVAL;
898 }
899
900 priv->variant = dev_get_driver_data(dev);
901
902 if (!priv->variant) {
903 printf("%s: Missing variant\n", __func__);
904 return -EINVAL;
905 }
906
907 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
908 if (ret) {
909 dev_err(dev, "failed to get TX clock\n");
910 return ret;
911 }
912
913 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
914 if (ret && ret != -ENOENT) {
915 dev_err(dev, "failed to get TX reset\n");
916 return ret;
917 }
918
919 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
920 if (offset < 0) {
921 debug("%s: cannot find syscon node\n", __func__);
922 return -EINVAL;
923 }
924
925 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
926 if (!reg) {
927 debug("%s: cannot find reg property in syscon node\n",
928 __func__);
929 return -EINVAL;
930 }
931 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
932 offset, reg);
933 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
934 debug("%s: Cannot find syscon base address\n", __func__);
935 return -EINVAL;
936 }
937
938 pdata->phy_interface = -1;
939 priv->phyaddr = -1;
940 priv->use_internal_phy = false;
941
942 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
943 if (offset < 0) {
944 debug("%s: Cannot find PHY address\n", __func__);
945 return -EINVAL;
946 }
947 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
948
949 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
950
951 if (phy_mode)
952 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
953 printf("phy interface%d\n", pdata->phy_interface);
954
955 if (pdata->phy_interface == -1) {
956 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
957 return -EINVAL;
958 }
959
960 if (priv->variant == H3_EMAC) {
961 ret = sun8i_handle_internal_phy(dev, priv);
962 if (ret)
963 return ret;
964 }
965
966 priv->interface = pdata->phy_interface;
967
968 if (!priv->use_internal_phy)
969 parse_phy_pins(dev);
970
971 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
972 "allwinner,tx-delay-ps", 0);
973 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
974 printf("%s: Invalid TX delay value %d\n", __func__,
975 sun8i_pdata->tx_delay_ps);
976
977 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
978 "allwinner,rx-delay-ps", 0);
979 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
980 printf("%s: Invalid RX delay value %d\n", __func__,
981 sun8i_pdata->rx_delay_ps);
982
983 #if CONFIG_IS_ENABLED(DM_GPIO)
984 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
985 "snps,reset-active-low"))
986 reset_flags |= GPIOD_ACTIVE_LOW;
987
988 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
989 &priv->reset_gpio, reset_flags);
990
991 if (ret == 0) {
992 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
993 "snps,reset-delays-us",
994 sun8i_pdata->reset_delays, 3);
995 } else if (ret == -ENOENT) {
996 ret = 0;
997 }
998 #endif
999
1000 return 0;
1001 }
1002
1003 static const struct udevice_id sun8i_emac_eth_ids[] = {
1004 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1005 {.compatible = "allwinner,sun50i-a64-emac",
1006 .data = (uintptr_t)A64_EMAC },
1007 {.compatible = "allwinner,sun8i-a83t-emac",
1008 .data = (uintptr_t)A83T_EMAC },
1009 {.compatible = "allwinner,sun8i-r40-gmac",
1010 .data = (uintptr_t)R40_GMAC },
1011 {.compatible = "allwinner,sun50i-h6-emac",
1012 .data = (uintptr_t)H6_EMAC },
1013 { }
1014 };
1015
1016 U_BOOT_DRIVER(eth_sun8i_emac) = {
1017 .name = "eth_sun8i_emac",
1018 .id = UCLASS_ETH,
1019 .of_match = sun8i_emac_eth_ids,
1020 .of_to_plat = sun8i_emac_eth_of_to_plat,
1021 .probe = sun8i_emac_eth_probe,
1022 .ops = &sun8i_emac_eth_ops,
1023 .priv_auto = sizeof(struct emac_eth_dev),
1024 .plat_auto = sizeof(struct sun8i_eth_pdata),
1025 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1026 };
1027