1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Waymo LLC
4 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2011 PetaLogix
6 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <log.h>
14 #include <net.h>
15 #include <malloc.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <phy.h>
19 #include <miiphy.h>
20 #include <wait_bit.h>
21 #include <linux/delay.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* Link setup */
26 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
27 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
28 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
29 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
30
31 /* Interrupt Status/Enable/Mask Registers bit definitions */
32 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
33 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
34
35 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
36 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
37
38 /* Transmitter Configuration (TC) Register bit definitions */
39 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
40
41 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
42
43 /* MDIO Management Configuration (MC) Register bit definitions */
44 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
45
46 /* MDIO Management Control Register (MCR) Register bit definitions */
47 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
48 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
49 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
50 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
51 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
52 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
53 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
54 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
55
56 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
57
58 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
59
60 /* DMA macros */
61 /* Bitmasks of XAXIDMA_CR_OFFSET register */
62 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
63 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
64
65 /* Bitmasks of XAXIDMA_SR_OFFSET register */
66 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
67
68 /* Bitmask for interrupts */
69 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
70 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
71 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
72
73 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
74 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
75 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
76
77 /* Bitmasks for XXV Ethernet MAC */
78 #define XXV_TC_TX_MASK 0x00000001
79 #define XXV_TC_FCS_MASK 0x00000002
80 #define XXV_RCW1_RX_MASK 0x00000001
81 #define XXV_RCW1_FCS_MASK 0x00000002
82
83 #define DMAALIGN 128
84 #define XXV_MIN_PKT_SIZE 60
85
86 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
87 static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
88
89 enum emac_variant {
90 EMAC_1G = 0,
91 EMAC_10G_25G = 1,
92 };
93
94 /* Reflect dma offsets */
95 struct axidma_reg {
96 u32 control; /* DMACR */
97 u32 status; /* DMASR */
98 u32 current; /* CURDESC low 32 bit */
99 u32 current_hi; /* CURDESC high 32 bit */
100 u32 tail; /* TAILDESC low 32 bit */
101 u32 tail_hi; /* TAILDESC high 32 bit */
102 };
103
104 /* Platform data structures */
105 struct axidma_plat {
106 struct eth_pdata eth_pdata;
107 struct axidma_reg *dmatx;
108 struct axidma_reg *dmarx;
109 int phyaddr;
110 u8 eth_hasnobuf;
111 int phy_of_handle;
112 enum emac_variant mactype;
113 };
114
115 /* Private driver structures */
116 struct axidma_priv {
117 struct axidma_reg *dmatx;
118 struct axidma_reg *dmarx;
119 int phyaddr;
120 struct axi_regs *iobase;
121 phy_interface_t interface;
122 struct phy_device *phydev;
123 struct mii_dev *bus;
124 u8 eth_hasnobuf;
125 int phy_of_handle;
126 enum emac_variant mactype;
127 };
128
129 /* BD descriptors */
130 struct axidma_bd {
131 u32 next_desc; /* Next descriptor pointer */
132 u32 next_desc_msb;
133 u32 buf_addr; /* Buffer address */
134 u32 buf_addr_msb;
135 u32 reserved3;
136 u32 reserved4;
137 u32 cntrl; /* Control */
138 u32 status; /* Status */
139 u32 app0;
140 u32 app1; /* TX start << 16 | insert */
141 u32 app2; /* TX csum seed */
142 u32 app3;
143 u32 app4;
144 u32 sw_id_offset;
145 u32 reserved5;
146 u32 reserved6;
147 };
148
149 /* Static BDs - driver uses only one BD */
150 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
151 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
152
153 struct axi_regs {
154 u32 reserved[3];
155 u32 is; /* 0xC: Interrupt status */
156 u32 reserved2;
157 u32 ie; /* 0x14: Interrupt enable */
158 u32 reserved3[251];
159 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
160 u32 tc; /* 0x408: Tx Configuration */
161 u32 reserved4;
162 u32 emmc; /* 0x410: EMAC mode configuration */
163 u32 reserved5[59];
164 u32 mdio_mc; /* 0x500: MII Management Config */
165 u32 mdio_mcr; /* 0x504: MII Management Control */
166 u32 mdio_mwd; /* 0x508: MII Management Write Data */
167 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
168 u32 reserved6[124];
169 u32 uaw0; /* 0x700: Unicast address word 0 */
170 u32 uaw1; /* 0x704: Unicast address word 1 */
171 };
172
173 struct xxv_axi_regs {
174 u32 gt_reset; /* 0x0 */
175 u32 reserved[2];
176 u32 tc; /* 0xC: Tx Configuration */
177 u32 reserved2;
178 u32 rcw1; /* 0x14: Rx Configuration Word 1 */
179 };
180
181 /* Use MII register 1 (MII status register) to detect PHY */
182 #define PHY_DETECT_REG 1
183
184 /*
185 * Mask used to verify certain PHY features (or register contents)
186 * in the register above:
187 * 0x1000: 10Mbps full duplex support
188 * 0x0800: 10Mbps half duplex support
189 * 0x0008: Auto-negotiation support
190 */
191 #define PHY_DETECT_MASK 0x1808
192
mdio_wait(struct axi_regs * regs)193 static inline int mdio_wait(struct axi_regs *regs)
194 {
195 u32 timeout = 200;
196
197 /* Wait till MDIO interface is ready to accept a new transaction. */
198 while (timeout && (!(readl(®s->mdio_mcr)
199 & XAE_MDIO_MCR_READY_MASK))) {
200 timeout--;
201 udelay(1);
202 }
203 if (!timeout) {
204 printf("%s: Timeout\n", __func__);
205 return 1;
206 }
207 return 0;
208 }
209
210 /**
211 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
212 * @bd: pointer to BD descriptor structure
213 * @desc: Address offset of DMA descriptors
214 *
215 * This function writes the value into the corresponding Axi DMA register.
216 */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)217 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
218 {
219 #if defined(CONFIG_PHYS_64BIT)
220 writeq((unsigned long)bd, desc);
221 #else
222 writel((u32)bd, desc);
223 #endif
224 }
225
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)226 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
227 u16 *val)
228 {
229 struct axi_regs *regs = priv->iobase;
230 u32 mdioctrlreg = 0;
231
232 if (mdio_wait(regs))
233 return 1;
234
235 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
236 XAE_MDIO_MCR_PHYAD_MASK) |
237 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
238 & XAE_MDIO_MCR_REGAD_MASK) |
239 XAE_MDIO_MCR_INITIATE_MASK |
240 XAE_MDIO_MCR_OP_READ_MASK;
241
242 writel(mdioctrlreg, ®s->mdio_mcr);
243
244 if (mdio_wait(regs))
245 return 1;
246
247 /* Read data */
248 *val = readl(®s->mdio_mrd);
249 return 0;
250 }
251
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)252 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
253 u32 data)
254 {
255 struct axi_regs *regs = priv->iobase;
256 u32 mdioctrlreg = 0;
257
258 if (mdio_wait(regs))
259 return 1;
260
261 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
262 XAE_MDIO_MCR_PHYAD_MASK) |
263 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
264 & XAE_MDIO_MCR_REGAD_MASK) |
265 XAE_MDIO_MCR_INITIATE_MASK |
266 XAE_MDIO_MCR_OP_WRITE_MASK;
267
268 /* Write data */
269 writel(data, ®s->mdio_mwd);
270
271 writel(mdioctrlreg, ®s->mdio_mcr);
272
273 if (mdio_wait(regs))
274 return 1;
275
276 return 0;
277 }
278
axiemac_phy_init(struct udevice * dev)279 static int axiemac_phy_init(struct udevice *dev)
280 {
281 u16 phyreg;
282 int i;
283 u32 ret;
284 struct axidma_priv *priv = dev_get_priv(dev);
285 struct axi_regs *regs = priv->iobase;
286 struct phy_device *phydev;
287
288 u32 supported = SUPPORTED_10baseT_Half |
289 SUPPORTED_10baseT_Full |
290 SUPPORTED_100baseT_Half |
291 SUPPORTED_100baseT_Full |
292 SUPPORTED_1000baseT_Half |
293 SUPPORTED_1000baseT_Full;
294
295 /* Set default MDIO divisor */
296 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
297
298 if (priv->phyaddr == -1) {
299 /* Detect the PHY address */
300 for (i = 31; i >= 0; i--) {
301 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
302 if (!ret && (phyreg != 0xFFFF) &&
303 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
304 /* Found a valid PHY address */
305 priv->phyaddr = i;
306 debug("axiemac: Found valid phy address, %x\n",
307 i);
308 break;
309 }
310 }
311 }
312
313 /* Interface - look at tsec */
314 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
315
316 phydev->supported &= supported;
317 phydev->advertising = phydev->supported;
318 priv->phydev = phydev;
319 if (priv->phy_of_handle)
320 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
321 phy_config(phydev);
322
323 return 0;
324 }
325
326 /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)327 static int setup_phy(struct udevice *dev)
328 {
329 u16 temp;
330 u32 speed, emmc_reg, ret;
331 struct axidma_priv *priv = dev_get_priv(dev);
332 struct axi_regs *regs = priv->iobase;
333 struct phy_device *phydev = priv->phydev;
334
335 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
336 /*
337 * In SGMII cases the isolate bit might set
338 * after DMA and ethernet resets and hence
339 * check and clear if set.
340 */
341 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
342 if (ret)
343 return 0;
344 if (temp & BMCR_ISOLATE) {
345 temp &= ~BMCR_ISOLATE;
346 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
347 if (ret)
348 return 0;
349 }
350 }
351
352 if (phy_startup(phydev)) {
353 printf("axiemac: could not initialize PHY %s\n",
354 phydev->dev->name);
355 return 0;
356 }
357 if (!phydev->link) {
358 printf("%s: No link.\n", phydev->dev->name);
359 return 0;
360 }
361
362 switch (phydev->speed) {
363 case 1000:
364 speed = XAE_EMMC_LINKSPD_1000;
365 break;
366 case 100:
367 speed = XAE_EMMC_LINKSPD_100;
368 break;
369 case 10:
370 speed = XAE_EMMC_LINKSPD_10;
371 break;
372 default:
373 return 0;
374 }
375
376 /* Setup the emac for the phy speed */
377 emmc_reg = readl(®s->emmc);
378 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
379 emmc_reg |= speed;
380
381 /* Write new speed setting out to Axi Ethernet */
382 writel(emmc_reg, ®s->emmc);
383
384 /*
385 * Setting the operating speed of the MAC needs a delay. There
386 * doesn't seem to be register to poll, so please consider this
387 * during your application design.
388 */
389 udelay(1);
390
391 return 1;
392 }
393
394 /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)395 static void axiemac_stop(struct udevice *dev)
396 {
397 struct axidma_priv *priv = dev_get_priv(dev);
398 u32 temp;
399
400 /* Stop the hardware */
401 temp = readl(&priv->dmatx->control);
402 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
403 writel(temp, &priv->dmatx->control);
404
405 temp = readl(&priv->dmarx->control);
406 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
407 writel(temp, &priv->dmarx->control);
408
409 debug("axiemac: Halted\n");
410 }
411
xxv_axi_ethernet_init(struct axidma_priv * priv)412 static int xxv_axi_ethernet_init(struct axidma_priv *priv)
413 {
414 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
415
416 writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1);
417 writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc);
418 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
419 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
420
421 return 0;
422 }
423
axi_ethernet_init(struct axidma_priv * priv)424 static int axi_ethernet_init(struct axidma_priv *priv)
425 {
426 struct axi_regs *regs = priv->iobase;
427 int err;
428
429 /*
430 * Check the status of the MgtRdy bit in the interrupt status
431 * registers. This must be done to allow the MGT clock to become stable
432 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
433 * will be valid until this bit is valid.
434 * The bit is always a 1 for all other PHY interfaces.
435 * Interrupt status and enable registers are not available in non
436 * processor mode and hence bypass in this mode
437 */
438 if (!priv->eth_hasnobuf) {
439 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
440 true, 200, false);
441 if (err) {
442 printf("%s: Timeout\n", __func__);
443 return 1;
444 }
445
446 /*
447 * Stop the device and reset HW
448 * Disable interrupts
449 */
450 writel(0, ®s->ie);
451 }
452
453 /* Disable the receiver */
454 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
455
456 /*
457 * Stopping the receiver in mid-packet causes a dropped packet
458 * indication from HW. Clear it.
459 */
460 if (!priv->eth_hasnobuf) {
461 /* Set the interrupt status register to clear the interrupt */
462 writel(XAE_INT_RXRJECT_MASK, ®s->is);
463 }
464
465 /* Setup HW */
466 /* Set default MDIO divisor */
467 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
468
469 debug("axiemac: InitHw done\n");
470 return 0;
471 }
472
axiemac_write_hwaddr(struct udevice * dev)473 static int axiemac_write_hwaddr(struct udevice *dev)
474 {
475 struct eth_pdata *pdata = dev_get_plat(dev);
476 struct axidma_priv *priv = dev_get_priv(dev);
477 struct axi_regs *regs = priv->iobase;
478
479 if (priv->mactype != EMAC_1G)
480 return 0;
481
482 /* Set the MAC address */
483 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
484 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
485 writel(val, ®s->uaw0);
486
487 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
488 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
489 writel(val, ®s->uaw1);
490 return 0;
491 }
492
493 /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)494 static void axi_dma_init(struct axidma_priv *priv)
495 {
496 u32 timeout = 500;
497
498 /* Reset the engine so the hardware starts from a known state */
499 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
500 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
501
502 /* At the initialization time, hardware should finish reset quickly */
503 while (timeout--) {
504 /* Check transmit/receive channel */
505 /* Reset is done when the reset bit is low */
506 if (!((readl(&priv->dmatx->control) |
507 readl(&priv->dmarx->control))
508 & XAXIDMA_CR_RESET_MASK)) {
509 break;
510 }
511 }
512 if (!timeout)
513 printf("%s: Timeout\n", __func__);
514 }
515
axiemac_start(struct udevice * dev)516 static int axiemac_start(struct udevice *dev)
517 {
518 struct axidma_priv *priv = dev_get_priv(dev);
519 u32 temp;
520
521 debug("axiemac: Init started\n");
522 /*
523 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
524 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
525 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
526 * would ensure a reset of AxiEthernet.
527 */
528 axi_dma_init(priv);
529
530 /* Initialize AxiEthernet hardware. */
531 if (priv->mactype == EMAC_1G) {
532 if (axi_ethernet_init(priv))
533 return -1;
534 } else {
535 if (xxv_axi_ethernet_init(priv))
536 return -1;
537 }
538
539 /* Disable all RX interrupts before RxBD space setup */
540 temp = readl(&priv->dmarx->control);
541 temp &= ~XAXIDMA_IRQ_ALL_MASK;
542 writel(temp, &priv->dmarx->control);
543
544 /* Start DMA RX channel. Now it's ready to receive data.*/
545 axienet_dma_write(&rx_bd, &priv->dmarx->current);
546
547 /* Setup the BD. */
548 memset(&rx_bd, 0, sizeof(rx_bd));
549 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
550 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
551 #if defined(CONFIG_PHYS_64BIT)
552 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
553 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
554 #endif
555 rx_bd.cntrl = sizeof(rxframe);
556 /* Flush the last BD so DMA core could see the updates */
557 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
558
559 /* It is necessary to flush rxframe because if you don't do it
560 * then cache can contain uninitialized data */
561 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
562
563 /* Start the hardware */
564 temp = readl(&priv->dmarx->control);
565 temp |= XAXIDMA_CR_RUNSTOP_MASK;
566 writel(temp, &priv->dmarx->control);
567
568 /* Rx BD is ready - start */
569 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
570
571 if (priv->mactype == EMAC_1G) {
572 struct axi_regs *regs = priv->iobase;
573 /* Enable TX */
574 writel(XAE_TC_TX_MASK, ®s->tc);
575 /* Enable RX */
576 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
577
578 /* PHY setup */
579 if (!setup_phy(dev)) {
580 axiemac_stop(dev);
581 return -1;
582 }
583 } else {
584 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
585 /* Enable TX */
586 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
587
588 /* Enable RX */
589 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
590 }
591
592 debug("axiemac: Init complete\n");
593 return 0;
594 }
595
axiemac_send(struct udevice * dev,void * ptr,int len)596 static int axiemac_send(struct udevice *dev, void *ptr, int len)
597 {
598 struct axidma_priv *priv = dev_get_priv(dev);
599 u32 timeout;
600
601 if (len > PKTSIZE_ALIGN)
602 len = PKTSIZE_ALIGN;
603
604 /* If size is less than min packet size, pad to min size */
605 if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) {
606 memset(txminframe, 0, XXV_MIN_PKT_SIZE);
607 memcpy(txminframe, ptr, len);
608 len = XXV_MIN_PKT_SIZE;
609 ptr = txminframe;
610 }
611
612 /* Flush packet to main memory to be trasfered by DMA */
613 flush_cache((phys_addr_t)ptr, len);
614
615 /* Setup Tx BD */
616 memset(&tx_bd, 0, sizeof(tx_bd));
617 /* At the end of the ring, link the last BD back to the top */
618 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
619 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
620 #if defined(CONFIG_PHYS_64BIT)
621 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
622 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
623 #endif
624 /* Save len */
625 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
626 XAXIDMA_BD_CTRL_TXEOF_MASK;
627
628 /* Flush the last BD so DMA core could see the updates */
629 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
630
631 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
632 u32 temp;
633 axienet_dma_write(&tx_bd, &priv->dmatx->current);
634 /* Start the hardware */
635 temp = readl(&priv->dmatx->control);
636 temp |= XAXIDMA_CR_RUNSTOP_MASK;
637 writel(temp, &priv->dmatx->control);
638 }
639
640 /* Start transfer */
641 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
642
643 /* Wait for transmission to complete */
644 debug("axiemac: Waiting for tx to be done\n");
645 timeout = 200;
646 while (timeout && (!(readl(&priv->dmatx->status) &
647 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
648 timeout--;
649 udelay(1);
650 }
651 if (!timeout) {
652 printf("%s: Timeout\n", __func__);
653 return 1;
654 }
655
656 debug("axiemac: Sending complete\n");
657 return 0;
658 }
659
isrxready(struct axidma_priv * priv)660 static int isrxready(struct axidma_priv *priv)
661 {
662 u32 status;
663
664 /* Read pending interrupts */
665 status = readl(&priv->dmarx->status);
666
667 /* Acknowledge pending interrupts */
668 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
669
670 /*
671 * If Reception done interrupt is asserted, call RX call back function
672 * to handle the processed BDs and then raise the according flag.
673 */
674 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
675 return 1;
676
677 return 0;
678 }
679
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)680 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
681 {
682 u32 length;
683 struct axidma_priv *priv = dev_get_priv(dev);
684 u32 temp;
685
686 /* Wait for an incoming packet */
687 if (!isrxready(priv))
688 return -1;
689
690 debug("axiemac: RX data ready\n");
691
692 /* Disable IRQ for a moment till packet is handled */
693 temp = readl(&priv->dmarx->control);
694 temp &= ~XAXIDMA_IRQ_ALL_MASK;
695 writel(temp, &priv->dmarx->control);
696 if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G)
697 length = rx_bd.app4 & 0xFFFF; /* max length mask */
698 else
699 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
700
701 #ifdef DEBUG
702 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
703 #endif
704
705 *packetp = rxframe;
706 return length;
707 }
708
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)709 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
710 {
711 struct axidma_priv *priv = dev_get_priv(dev);
712
713 #ifdef DEBUG
714 /* It is useful to clear buffer to be sure that it is consistent */
715 memset(rxframe, 0, sizeof(rxframe));
716 #endif
717 /* Setup RxBD */
718 /* Clear the whole buffer and setup it again - all flags are cleared */
719 memset(&rx_bd, 0, sizeof(rx_bd));
720 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
721 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
722 #if defined(CONFIG_PHYS_64BIT)
723 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
724 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
725 #endif
726 rx_bd.cntrl = sizeof(rxframe);
727
728 /* Write bd to HW */
729 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
730
731 /* It is necessary to flush rxframe because if you don't do it
732 * then cache will contain previous packet */
733 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
734
735 /* Rx BD is ready - start again */
736 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
737
738 debug("axiemac: RX completed, framelength = %d\n", length);
739
740 return 0;
741 }
742
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)743 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
744 int devad, int reg)
745 {
746 int ret;
747 u16 value;
748
749 ret = phyread(bus->priv, addr, reg, &value);
750 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
751 value, ret);
752 return value;
753 }
754
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)755 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
756 int reg, u16 value)
757 {
758 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
759 return phywrite(bus->priv, addr, reg, value);
760 }
761
axi_emac_probe(struct udevice * dev)762 static int axi_emac_probe(struct udevice *dev)
763 {
764 struct axidma_plat *plat = dev_get_plat(dev);
765 struct eth_pdata *pdata = &plat->eth_pdata;
766 struct axidma_priv *priv = dev_get_priv(dev);
767 int ret;
768
769 priv->iobase = (struct axi_regs *)pdata->iobase;
770 priv->dmatx = plat->dmatx;
771 /* RX channel offset is 0x30 */
772 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
773 priv->mactype = plat->mactype;
774
775 if (priv->mactype == EMAC_1G) {
776 priv->eth_hasnobuf = plat->eth_hasnobuf;
777 priv->phyaddr = plat->phyaddr;
778 priv->phy_of_handle = plat->phy_of_handle;
779 priv->interface = pdata->phy_interface;
780
781 priv->bus = mdio_alloc();
782 priv->bus->read = axiemac_miiphy_read;
783 priv->bus->write = axiemac_miiphy_write;
784 priv->bus->priv = priv;
785
786 ret = mdio_register_seq(priv->bus, dev_seq(dev));
787 if (ret)
788 return ret;
789
790 axiemac_phy_init(dev);
791 }
792
793 return 0;
794 }
795
axi_emac_remove(struct udevice * dev)796 static int axi_emac_remove(struct udevice *dev)
797 {
798 struct axidma_priv *priv = dev_get_priv(dev);
799
800 if (priv->mactype == EMAC_1G) {
801 free(priv->phydev);
802 mdio_unregister(priv->bus);
803 mdio_free(priv->bus);
804 }
805
806 return 0;
807 }
808
809 static const struct eth_ops axi_emac_ops = {
810 .start = axiemac_start,
811 .send = axiemac_send,
812 .recv = axiemac_recv,
813 .free_pkt = axiemac_free_pkt,
814 .stop = axiemac_stop,
815 .write_hwaddr = axiemac_write_hwaddr,
816 };
817
axi_emac_of_to_plat(struct udevice * dev)818 static int axi_emac_of_to_plat(struct udevice *dev)
819 {
820 struct axidma_plat *plat = dev_get_plat(dev);
821 struct eth_pdata *pdata = &plat->eth_pdata;
822 int node = dev_of_offset(dev);
823 int offset = 0;
824 const char *phy_mode;
825
826 pdata->iobase = dev_read_addr(dev);
827 plat->mactype = dev_get_driver_data(dev);
828
829 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
830 "axistream-connected");
831 if (offset <= 0) {
832 printf("%s: axistream is not found\n", __func__);
833 return -EINVAL;
834 }
835 plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
836 offset, "reg");
837 if (!plat->dmatx) {
838 printf("%s: axi_dma register space not found\n", __func__);
839 return -EINVAL;
840 }
841
842 if (plat->mactype == EMAC_1G) {
843 plat->phyaddr = -1;
844
845 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
846 "phy-handle");
847 if (offset > 0) {
848 plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
849 "reg", -1);
850 plat->phy_of_handle = offset;
851 }
852
853 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
854 if (phy_mode)
855 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
856 if (pdata->phy_interface == -1) {
857 printf("%s: Invalid PHY interface '%s'\n", __func__,
858 phy_mode);
859 return -EINVAL;
860 }
861
862 plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
863 "xlnx,eth-hasnobuf");
864 }
865
866 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
867 plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
868
869 return 0;
870 }
871
872 static const struct udevice_id axi_emac_ids[] = {
873 { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G },
874 { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G },
875 { }
876 };
877
878 U_BOOT_DRIVER(axi_emac) = {
879 .name = "axi_emac",
880 .id = UCLASS_ETH,
881 .of_match = axi_emac_ids,
882 .of_to_plat = axi_emac_of_to_plat,
883 .probe = axi_emac_probe,
884 .remove = axi_emac_remove,
885 .ops = &axi_emac_ops,
886 .priv_auto = sizeof(struct axidma_priv),
887 .plat_auto = sizeof(struct axidma_plat),
888 };
889