1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale i.MX6 PCI Express Root-Complex driver
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 *
7 * Based on upstream Linux kernel driver:
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 */
11
12 #include <common.h>
13 #include <init.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <pci.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/gpio.h>
21 #include <asm/io.h>
22 #include <dm.h>
23 #include <linux/delay.h>
24 #include <linux/sizes.h>
25 #include <errno.h>
26 #include <asm/arch/sys_proto.h>
27
28 #define PCI_ACCESS_READ 0
29 #define PCI_ACCESS_WRITE 1
30
31 #ifdef CONFIG_MX6SX
32 #define MX6_DBI_ADDR 0x08ffc000
33 #define MX6_IO_ADDR 0x08000000
34 #define MX6_MEM_ADDR 0x08100000
35 #define MX6_ROOT_ADDR 0x08f00000
36 #else
37 #define MX6_DBI_ADDR 0x01ffc000
38 #define MX6_IO_ADDR 0x01000000
39 #define MX6_MEM_ADDR 0x01100000
40 #define MX6_ROOT_ADDR 0x01f00000
41 #endif
42 #define MX6_DBI_SIZE 0x4000
43 #define MX6_IO_SIZE 0x100000
44 #define MX6_MEM_SIZE 0xe00000
45 #define MX6_ROOT_SIZE 0xfc000
46
47 /* PCIe Port Logic registers (memory-mapped) */
48 #define PL_OFFSET 0x700
49 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
50 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
51 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
52 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
53 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
54 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
55 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
56
57 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
58 #define PCIE_PHY_CTRL_DATA_LOC 0
59 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
60 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
61 #define PCIE_PHY_CTRL_WR_LOC 18
62 #define PCIE_PHY_CTRL_RD_LOC 19
63
64 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
65 #define PCIE_PHY_STAT_DATA_LOC 0
66 #define PCIE_PHY_STAT_ACK_LOC 16
67
68 /* PHY registers (not memory-mapped) */
69 #define PCIE_PHY_RX_ASIC_OUT 0x100D
70
71 #define PHY_RX_OVRD_IN_LO 0x1005
72 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
73 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
74
75 #define PCIE_PHY_PUP_REQ (1 << 7)
76
77 /* iATU registers */
78 #define PCIE_ATU_VIEWPORT 0x900
79 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
80 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
81 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
82 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
83 #define PCIE_ATU_CR1 0x904
84 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
85 #define PCIE_ATU_TYPE_IO (0x2 << 0)
86 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
87 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
88 #define PCIE_ATU_CR2 0x908
89 #define PCIE_ATU_ENABLE (0x1 << 31)
90 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
91 #define PCIE_ATU_LOWER_BASE 0x90C
92 #define PCIE_ATU_UPPER_BASE 0x910
93 #define PCIE_ATU_LIMIT 0x914
94 #define PCIE_ATU_LOWER_TARGET 0x918
95 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
96 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
97 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
98 #define PCIE_ATU_UPPER_TARGET 0x91C
99
100 struct imx_pcie_priv {
101 void __iomem *dbi_base;
102 void __iomem *cfg_base;
103 struct gpio_desc reset_gpio;
104 bool reset_active_high;
105 };
106
107 /*
108 * PHY access functions
109 */
pcie_phy_poll_ack(void __iomem * dbi_base,int exp_val)110 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
111 {
112 u32 val;
113 u32 max_iterations = 10;
114 u32 wait_counter = 0;
115
116 do {
117 val = readl(dbi_base + PCIE_PHY_STAT);
118 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
119 wait_counter++;
120
121 if (val == exp_val)
122 return 0;
123
124 udelay(1);
125 } while (wait_counter < max_iterations);
126
127 return -ETIMEDOUT;
128 }
129
pcie_phy_wait_ack(void __iomem * dbi_base,int addr)130 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
131 {
132 u32 val;
133 int ret;
134
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 writel(val, dbi_base + PCIE_PHY_CTRL);
137
138 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
139 writel(val, dbi_base + PCIE_PHY_CTRL);
140
141 ret = pcie_phy_poll_ack(dbi_base, 1);
142 if (ret)
143 return ret;
144
145 val = addr << PCIE_PHY_CTRL_DATA_LOC;
146 writel(val, dbi_base + PCIE_PHY_CTRL);
147
148 ret = pcie_phy_poll_ack(dbi_base, 0);
149 if (ret)
150 return ret;
151
152 return 0;
153 }
154
155 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(void __iomem * dbi_base,int addr,int * data)156 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
157 {
158 u32 val, phy_ctl;
159 int ret;
160
161 ret = pcie_phy_wait_ack(dbi_base, addr);
162 if (ret)
163 return ret;
164
165 /* assert Read signal */
166 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
167 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
168
169 ret = pcie_phy_poll_ack(dbi_base, 1);
170 if (ret)
171 return ret;
172
173 val = readl(dbi_base + PCIE_PHY_STAT);
174 *data = val & 0xffff;
175
176 /* deassert Read signal */
177 writel(0x00, dbi_base + PCIE_PHY_CTRL);
178
179 ret = pcie_phy_poll_ack(dbi_base, 0);
180 if (ret)
181 return ret;
182
183 return 0;
184 }
185
pcie_phy_write(void __iomem * dbi_base,int addr,int data)186 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
187 {
188 u32 var;
189 int ret;
190
191 /* write addr */
192 /* cap addr */
193 ret = pcie_phy_wait_ack(dbi_base, addr);
194 if (ret)
195 return ret;
196
197 var = data << PCIE_PHY_CTRL_DATA_LOC;
198 writel(var, dbi_base + PCIE_PHY_CTRL);
199
200 /* capture data */
201 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
202 writel(var, dbi_base + PCIE_PHY_CTRL);
203
204 ret = pcie_phy_poll_ack(dbi_base, 1);
205 if (ret)
206 return ret;
207
208 /* deassert cap data */
209 var = data << PCIE_PHY_CTRL_DATA_LOC;
210 writel(var, dbi_base + PCIE_PHY_CTRL);
211
212 /* wait for ack de-assertion */
213 ret = pcie_phy_poll_ack(dbi_base, 0);
214 if (ret)
215 return ret;
216
217 /* assert wr signal */
218 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
219 writel(var, dbi_base + PCIE_PHY_CTRL);
220
221 /* wait for ack */
222 ret = pcie_phy_poll_ack(dbi_base, 1);
223 if (ret)
224 return ret;
225
226 /* deassert wr signal */
227 var = data << PCIE_PHY_CTRL_DATA_LOC;
228 writel(var, dbi_base + PCIE_PHY_CTRL);
229
230 /* wait for ack de-assertion */
231 ret = pcie_phy_poll_ack(dbi_base, 0);
232 if (ret)
233 return ret;
234
235 writel(0x0, dbi_base + PCIE_PHY_CTRL);
236
237 return 0;
238 }
239
imx6_pcie_link_up(struct imx_pcie_priv * priv)240 static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
241 {
242 u32 rc, ltssm;
243 int rx_valid, temp;
244
245 /* link is debug bit 36, debug register 1 starts at bit 32 */
246 rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
247 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
248 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
249 return -EAGAIN;
250
251 /*
252 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
253 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
254 * If (MAC/LTSSM.state == Recovery.RcvrLock)
255 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
256 * to gen2 is stuck
257 */
258 pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
259 ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
260
261 if (rx_valid & 0x01)
262 return 0;
263
264 if (ltssm != 0x0d)
265 return 0;
266
267 printf("transition to gen2 is stuck, reset PHY!\n");
268
269 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
270 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
271 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
272
273 udelay(3000);
274
275 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
276 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
277 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
278
279 return 0;
280 }
281
282 /*
283 * iATU region setup
284 */
imx_pcie_regions_setup(struct imx_pcie_priv * priv)285 static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
286 {
287 /*
288 * i.MX6 defines 16MB in the AXI address map for PCIe.
289 *
290 * That address space excepted the pcie registers is
291 * split and defined into different regions by iATU,
292 * with sizes and offsets as follows:
293 *
294 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
295 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
296 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
297 */
298
299 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
300 setbits_le32(priv->dbi_base + PCI_COMMAND,
301 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
302
303 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
304 setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
305 PCI_CLASS_BRIDGE_PCI << 16);
306
307 /* Region #0 is used for Outbound CFG space access. */
308 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
309
310 writel(lower_32_bits((uintptr_t)priv->cfg_base),
311 priv->dbi_base + PCIE_ATU_LOWER_BASE);
312 writel(upper_32_bits((uintptr_t)priv->cfg_base),
313 priv->dbi_base + PCIE_ATU_UPPER_BASE);
314 writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
315 priv->dbi_base + PCIE_ATU_LIMIT);
316
317 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
318 writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
319 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
320 writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
321
322 return 0;
323 }
324
325 /*
326 * PCI Express accessors
327 */
get_bus_address(struct imx_pcie_priv * priv,pci_dev_t d,int where)328 static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
329 pci_dev_t d, int where)
330 {
331 void __iomem *va_address;
332
333 /* Reconfigure Region #0 */
334 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
335
336 if (PCI_BUS(d) < 2)
337 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
338 else
339 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
340
341 if (PCI_BUS(d) == 0) {
342 va_address = priv->dbi_base;
343 } else {
344 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
345 va_address = priv->cfg_base;
346 }
347
348 va_address += (where & ~0x3);
349
350 return va_address;
351 }
352
imx_pcie_addr_valid(pci_dev_t d)353 static int imx_pcie_addr_valid(pci_dev_t d)
354 {
355 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
356 return -EINVAL;
357 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
358 return -EINVAL;
359 return 0;
360 }
361
362 /*
363 * Replace the original ARM DABT handler with a simple jump-back one.
364 *
365 * The problem here is that if we have a PCIe bridge attached to this PCIe
366 * controller, but no PCIe device is connected to the bridges' downstream
367 * port, the attempt to read/write from/to the config space will produce
368 * a DABT. This is a behavior of the controller and can not be disabled
369 * unfortuatelly.
370 *
371 * To work around the problem, we backup the current DABT handler address
372 * and replace it with our own DABT handler, which only bounces right back
373 * into the code.
374 */
imx_pcie_fix_dabt_handler(bool set)375 static void imx_pcie_fix_dabt_handler(bool set)
376 {
377 extern uint32_t *_data_abort;
378 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
379
380 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
381 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
382
383 static uint32_t data_abort_backup;
384
385 if (set) {
386 data_abort_backup = *data_abort_addr;
387 *data_abort_addr = data_abort_bounce_addr;
388 } else {
389 *data_abort_addr = data_abort_backup;
390 }
391 }
392
imx_pcie_read_cfg(struct imx_pcie_priv * priv,pci_dev_t d,int where,u32 * val)393 static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
394 int where, u32 *val)
395 {
396 void __iomem *va_address;
397 int ret;
398
399 ret = imx_pcie_addr_valid(d);
400 if (ret) {
401 *val = 0xffffffff;
402 return 0;
403 }
404
405 va_address = get_bus_address(priv, d, where);
406
407 /*
408 * Read the PCIe config space. We must replace the DABT handler
409 * here in case we got data abort from the PCIe controller, see
410 * imx_pcie_fix_dabt_handler() description. Note that writing the
411 * "val" with valid value is also imperative here as in case we
412 * did got DABT, the val would contain random value.
413 */
414 imx_pcie_fix_dabt_handler(true);
415 writel(0xffffffff, val);
416 *val = readl(va_address);
417 imx_pcie_fix_dabt_handler(false);
418
419 return 0;
420 }
421
imx_pcie_write_cfg(struct imx_pcie_priv * priv,pci_dev_t d,int where,u32 val)422 static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
423 int where, u32 val)
424 {
425 void __iomem *va_address = NULL;
426 int ret;
427
428 ret = imx_pcie_addr_valid(d);
429 if (ret)
430 return ret;
431
432 va_address = get_bus_address(priv, d, where);
433
434 /*
435 * Write the PCIe config space. We must replace the DABT handler
436 * here in case we got data abort from the PCIe controller, see
437 * imx_pcie_fix_dabt_handler() description.
438 */
439 imx_pcie_fix_dabt_handler(true);
440 writel(val, va_address);
441 imx_pcie_fix_dabt_handler(false);
442
443 return 0;
444 }
445
446 /*
447 * Initial bus setup
448 */
imx6_pcie_assert_core_reset(struct imx_pcie_priv * priv,bool prepare_for_boot)449 static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
450 bool prepare_for_boot)
451 {
452 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
453
454 if (is_mx6dqp())
455 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
456
457 #if defined(CONFIG_MX6SX)
458 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
459
460 /* SSP_EN is not used on MX6SX anymore */
461 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
462 /* Force PCIe PHY reset */
463 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
464 /* Power up PCIe PHY */
465 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
466 #else
467 /*
468 * If the bootloader already enabled the link we need some special
469 * handling to get the core back into a state where it is safe to
470 * touch it for configuration. As there is no dedicated reset signal
471 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
472 * state before completely disabling LTSSM, which is a prerequisite
473 * for core configuration.
474 *
475 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
476 * indication that the bootloader activated the link.
477 */
478 if ((is_mx6dq() || is_mx6sdl()) && prepare_for_boot) {
479 u32 val, gpr1, gpr12;
480
481 gpr1 = readl(&iomuxc_regs->gpr[1]);
482 gpr12 = readl(&iomuxc_regs->gpr[12]);
483 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
484 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
485 val = readl(priv->dbi_base + PCIE_PL_PFLR);
486 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
487 val |= PCIE_PL_PFLR_FORCE_LINK;
488
489 imx_pcie_fix_dabt_handler(true);
490 writel(val, priv->dbi_base + PCIE_PL_PFLR);
491 imx_pcie_fix_dabt_handler(false);
492
493 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
494 writel(val, &iomuxc_regs->gpr[12]);
495 }
496 }
497 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
498 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
499 #endif
500
501 return 0;
502 }
503
imx6_pcie_init_phy(void)504 static int imx6_pcie_init_phy(void)
505 {
506 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
507
508 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
509
510 clrsetbits_le32(&iomuxc_regs->gpr[12],
511 IOMUXC_GPR12_DEVICE_TYPE_MASK,
512 IOMUXC_GPR12_DEVICE_TYPE_RC);
513 clrsetbits_le32(&iomuxc_regs->gpr[12],
514 IOMUXC_GPR12_LOS_LEVEL_MASK,
515 IOMUXC_GPR12_LOS_LEVEL_9);
516
517 #ifdef CONFIG_MX6SX
518 clrsetbits_le32(&iomuxc_regs->gpr[12],
519 IOMUXC_GPR12_RX_EQ_MASK,
520 IOMUXC_GPR12_RX_EQ_2);
521 #endif
522
523 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
524 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
525 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
526 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
527 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
528 &iomuxc_regs->gpr[8]);
529
530 return 0;
531 }
532
imx6_pcie_toggle_power(void)533 __weak int imx6_pcie_toggle_power(void)
534 {
535 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
536 gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
537 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
538 mdelay(20);
539 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
540 mdelay(20);
541 gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
542 #endif
543 return 0;
544 }
545
imx6_pcie_toggle_reset(struct gpio_desc * gpio,bool active_high)546 __weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
547 {
548 /*
549 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
550 * for detailed understanding of the PCIe CR reset logic.
551 *
552 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
553 * design does not conform to the specification. You must wait at
554 * least 20 ms after de-asserting the #PERST so the EP device can
555 * do self-initialisation.
556 *
557 * In case your #PERST pin is connected to a plain GPIO pin of the
558 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
559 * configuration file and the condition below will handle the rest
560 * of the reset toggling.
561 *
562 * In case your #PERST toggling logic is more complex, for example
563 * connected via CPLD or somesuch, you can override this function
564 * in your board file and implement reset logic as needed. You must
565 * not forget to wait at least 20 ms after de-asserting #PERST in
566 * this case either though.
567 *
568 * In case your #PERST line of the PCIe EP device is not connected
569 * at all, your design is broken and you should fix your design,
570 * otherwise you will observe problems like for example the link
571 * not coming up after rebooting the system back from running Linux
572 * that uses the PCIe as well OR the PCIe link might not come up in
573 * Linux at all in the first place since it's in some non-reset
574 * state due to being previously used in U-Boot.
575 */
576 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
577 gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
578 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
579 mdelay(20);
580 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
581 mdelay(20);
582 gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
583 #else
584 if (dm_gpio_is_valid(gpio)) {
585 /* Assert PERST# for 20ms then de-assert */
586 dm_gpio_set_value(gpio, active_high ? 0 : 1);
587 mdelay(20);
588 dm_gpio_set_value(gpio, active_high ? 1 : 0);
589 mdelay(20);
590 } else {
591 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
592 }
593 #endif
594 return 0;
595 }
596
imx6_pcie_deassert_core_reset(struct imx_pcie_priv * priv)597 static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
598 {
599 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
600
601 imx6_pcie_toggle_power();
602
603 enable_pcie_clock();
604
605 if (is_mx6dqp())
606 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
607
608 /*
609 * Wait for the clock to settle a bit, when the clock are sourced
610 * from the CPU, we need about 30 ms to settle.
611 */
612 mdelay(50);
613
614 #if defined(CONFIG_MX6SX)
615 /* SSP_EN is not used on MX6SX anymore */
616 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
617 /* Clear PCIe PHY reset bit */
618 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
619 #else
620 /* Enable PCIe */
621 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
622 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
623 #endif
624
625 imx6_pcie_toggle_reset(&priv->reset_gpio, priv->reset_active_high);
626
627 return 0;
628 }
629
imx_pcie_link_up(struct imx_pcie_priv * priv)630 static int imx_pcie_link_up(struct imx_pcie_priv *priv)
631 {
632 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
633 uint32_t tmp;
634 int count = 0;
635
636 imx6_pcie_assert_core_reset(priv, false);
637 imx6_pcie_init_phy();
638 imx6_pcie_deassert_core_reset(priv);
639
640 imx_pcie_regions_setup(priv);
641
642 /*
643 * By default, the subordinate is set equally to the secondary
644 * bus (0x01) when the RC boots.
645 * This means that theoretically, only bus 1 is reachable from the RC.
646 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
647 * devices will be detected if the enumeration is applied strictly.
648 */
649 tmp = readl(priv->dbi_base + 0x18);
650 tmp |= (0xff << 16);
651 writel(tmp, priv->dbi_base + 0x18);
652
653 /*
654 * FIXME: Force the PCIe RC to Gen1 operation
655 * The RC must be forced into Gen1 mode before bringing the link
656 * up, otherwise no downstream devices are detected. After the
657 * link is up, a managed Gen1->Gen2 transition can be initiated.
658 */
659 tmp = readl(priv->dbi_base + 0x7c);
660 tmp &= ~0xf;
661 tmp |= 0x1;
662 writel(tmp, priv->dbi_base + 0x7c);
663
664 /* LTSSM enable, starting link. */
665 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
666
667 while (!imx6_pcie_link_up(priv)) {
668 udelay(10);
669 count++;
670 if (count >= 4000) {
671 #ifdef CONFIG_PCI_SCAN_SHOW
672 puts("PCI: pcie phy link never came up\n");
673 #endif
674 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
675 readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
676 readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
677 return -EINVAL;
678 }
679 }
680
681 return 0;
682 }
683
imx_pcie_dm_read_config(const struct udevice * dev,pci_dev_t bdf,uint offset,ulong * value,enum pci_size_t size)684 static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
685 uint offset, ulong *value,
686 enum pci_size_t size)
687 {
688 struct imx_pcie_priv *priv = dev_get_priv(dev);
689 u32 tmpval;
690 int ret;
691
692 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
693 if (ret)
694 return ret;
695
696 *value = pci_conv_32_to_size(tmpval, offset, size);
697 return 0;
698 }
699
imx_pcie_dm_write_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)700 static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
701 uint offset, ulong value,
702 enum pci_size_t size)
703 {
704 struct imx_pcie_priv *priv = dev_get_priv(dev);
705 u32 tmpval, newval;
706 int ret;
707
708 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
709 if (ret)
710 return ret;
711
712 newval = pci_conv_size_to_32(tmpval, value, offset, size);
713 return imx_pcie_write_cfg(priv, bdf, offset, newval);
714 }
715
imx_pcie_dm_probe(struct udevice * dev)716 static int imx_pcie_dm_probe(struct udevice *dev)
717 {
718 struct imx_pcie_priv *priv = dev_get_priv(dev);
719
720 /* if PERST# valid from dt then assert it */
721 gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
722 GPIOD_IS_OUT);
723 priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
724 if (dm_gpio_is_valid(&priv->reset_gpio)) {
725 dm_gpio_set_value(&priv->reset_gpio,
726 priv->reset_active_high ? 0 : 1);
727 }
728
729 return imx_pcie_link_up(priv);
730 }
731
imx_pcie_dm_remove(struct udevice * dev)732 static int imx_pcie_dm_remove(struct udevice *dev)
733 {
734 struct imx_pcie_priv *priv = dev_get_priv(dev);
735
736 imx6_pcie_assert_core_reset(priv, true);
737
738 return 0;
739 }
740
imx_pcie_of_to_plat(struct udevice * dev)741 static int imx_pcie_of_to_plat(struct udevice *dev)
742 {
743 struct imx_pcie_priv *priv = dev_get_priv(dev);
744
745 priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
746 priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
747 if (!priv->dbi_base || !priv->cfg_base)
748 return -EINVAL;
749
750 return 0;
751 }
752
753 static const struct dm_pci_ops imx_pcie_ops = {
754 .read_config = imx_pcie_dm_read_config,
755 .write_config = imx_pcie_dm_write_config,
756 };
757
758 static const struct udevice_id imx_pcie_ids[] = {
759 { .compatible = "fsl,imx6q-pcie" },
760 { .compatible = "fsl,imx6sx-pcie" },
761 { }
762 };
763
764 U_BOOT_DRIVER(imx_pcie) = {
765 .name = "imx_pcie",
766 .id = UCLASS_PCI,
767 .of_match = imx_pcie_ids,
768 .ops = &imx_pcie_ops,
769 .probe = imx_pcie_dm_probe,
770 .remove = imx_pcie_dm_remove,
771 .of_to_plat = imx_pcie_of_to_plat,
772 .priv_auto = sizeof(struct imx_pcie_priv),
773 .flags = DM_FLAG_OS_PREPARE,
774 };
775