1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCI Endpoint uclass
4 *
5 * Based on Linux PCI-EP driver written by
6 * Kishon Vijay Abraham I <kishon@ti.com>
7 *
8 * Copyright (c) 2019
9 * Written by Ramon Fried <ramon.fried@gmail.com>
10 */
11
12 #define LOG_CATEGORY UCLASS_PCI_EP
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <asm/global_data.h>
18 #include <linux/log2.h>
19 #include <pci_ep.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
pci_ep_write_header(struct udevice * dev,uint fn,struct pci_ep_header * hdr)23 int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
24 {
25 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
26
27 if (!ops->write_header)
28 return -ENOSYS;
29
30 return ops->write_header(dev, fn, hdr);
31 }
32
pci_ep_read_header(struct udevice * dev,uint fn,struct pci_ep_header * hdr)33 int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
34 {
35 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
36
37 if (!ops->read_header)
38 return -ENOSYS;
39
40 return ops->read_header(dev, fn, hdr);
41 }
42
pci_ep_set_bar(struct udevice * dev,uint func_no,struct pci_bar * ep_bar)43 int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
44 {
45 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
46 int flags = ep_bar->flags;
47
48 /* Some basic bar validity checks */
49 if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
50 return -EINVAL;
51
52 if ((ep_bar->barno == BAR_5 &&
53 (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
54 ((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
55 (flags & PCI_BASE_ADDRESS_IO_MASK)) ||
56 (upper_32_bits(ep_bar->size) &&
57 !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
58 return -EINVAL;
59
60 if (!ops->set_bar)
61 return -ENOSYS;
62
63 return ops->set_bar(dev, func_no, ep_bar);
64 }
65
pci_ep_read_bar(struct udevice * dev,uint func_no,struct pci_bar * ep_bar,enum pci_barno barno)66 int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
67 enum pci_barno barno)
68 {
69 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
70
71 /* Some basic bar validity checks */
72 if (barno > BAR_5 || barno < BAR_0)
73 return -EINVAL;
74
75 if (!ops->read_bar)
76 return -ENOSYS;
77
78 return ops->read_bar(dev, func_no, ep_bar, barno);
79 }
80
pci_ep_clear_bar(struct udevice * dev,uint func_num,enum pci_barno bar)81 int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
82 {
83 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
84
85 if (!ops->clear_bar)
86 return -ENOSYS;
87
88 return ops->clear_bar(dev, func_num, bar);
89 }
90
pci_ep_map_addr(struct udevice * dev,uint func_no,phys_addr_t addr,u64 pci_addr,size_t size)91 int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
92 u64 pci_addr, size_t size)
93 {
94 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
95
96 if (!ops->map_addr)
97 return -ENOSYS;
98
99 return ops->map_addr(dev, func_no, addr, pci_addr, size);
100 }
101
pci_ep_unmap_addr(struct udevice * dev,uint func_no,phys_addr_t addr)102 int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
103 {
104 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
105
106 if (!ops->unmap_addr)
107 return -ENOSYS;
108
109 return ops->unmap_addr(dev, func_no, addr);
110 }
111
pci_ep_set_msi(struct udevice * dev,uint func_no,uint interrupts)112 int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
113 {
114 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
115 uint encode_int;
116
117 if (interrupts > 32)
118 return -EINVAL;
119
120 if (!ops->set_msi)
121 return -ENOSYS;
122
123 /* MSI spec permits allocation of
124 * only 1, 2, 4, 8, 16, 32 interrupts
125 */
126 encode_int = order_base_2(interrupts);
127
128 return ops->set_msi(dev, func_no, encode_int);
129 }
130
pci_ep_get_msi(struct udevice * dev,uint func_no)131 int pci_ep_get_msi(struct udevice *dev, uint func_no)
132 {
133 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
134 int interrupt;
135
136 if (!ops->get_msi)
137 return -ENOSYS;
138
139 interrupt = ops->get_msi(dev, func_no);
140
141 if (interrupt < 0)
142 return 0;
143
144 /* Translate back from order base 2*/
145 interrupt = 1 << interrupt;
146
147 return interrupt;
148 }
149
pci_ep_set_msix(struct udevice * dev,uint func_no,uint interrupts)150 int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
151 {
152 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
153
154 if (interrupts < 1 || interrupts > 2048)
155 return -EINVAL;
156
157 if (!ops->set_msix)
158 return -ENOSYS;
159
160 return ops->set_msix(dev, func_no, interrupts - 1);
161 }
162
pci_ep_get_msix(struct udevice * dev,uint func_no)163 int pci_ep_get_msix(struct udevice *dev, uint func_no)
164 {
165 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
166 int interrupt;
167
168 if (!ops->get_msix)
169 return -ENOSYS;
170
171 interrupt = ops->get_msix(dev, func_no);
172
173 if (interrupt < 0)
174 return 0;
175
176 return interrupt + 1;
177 }
178
pci_ep_raise_irq(struct udevice * dev,uint func_no,enum pci_ep_irq_type type,uint interrupt_num)179 int pci_ep_raise_irq(struct udevice *dev, uint func_no,
180 enum pci_ep_irq_type type, uint interrupt_num)
181 {
182 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
183
184 if (!ops->raise_irq)
185 return -ENOSYS;
186
187 return ops->raise_irq(dev, func_no, type, interrupt_num);
188 }
189
pci_ep_start(struct udevice * dev)190 int pci_ep_start(struct udevice *dev)
191 {
192 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
193
194 if (!ops->start)
195 return -ENOSYS;
196
197 return ops->start(dev);
198 }
199
pci_ep_stop(struct udevice * dev)200 int pci_ep_stop(struct udevice *dev)
201 {
202 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
203
204 if (!ops->stop)
205 return -ENOSYS;
206
207 return ops->stop(dev);
208 }
209
210 UCLASS_DRIVER(pci_ep) = {
211 .id = UCLASS_PCI_EP,
212 .name = "pci_ep",
213 .flags = DM_UC_FLAG_SEQ_ALIAS,
214 };
215
pci_ep_init(void)216 int pci_ep_init(void)
217 {
218 struct udevice *dev;
219
220 for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
221 dev;
222 uclass_next_device_check(&dev)) {
223 ;
224 }
225
226 return 0;
227 }
228