1 /*
2  * Allwinner sun4i USB PHY driver
3  *
4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
7  *
8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #include <common.h>
14 #include <clk.h>
15 #include <dm.h>
16 #include <log.h>
17 #include <dm/device.h>
18 #include <generic-phy.h>
19 #include <phy-sun4i-usb.h>
20 #include <reset.h>
21 #include <asm/gpio.h>
22 #include <asm/io.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/cpu.h>
25 #include <dm/device_compat.h>
26 #include <linux/bitops.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <power/regulator.h>
30 
31 #define REG_ISCR			0x00
32 #define REG_PHYCTL_A10			0x04
33 #define REG_PHYBIST			0x08
34 #define REG_PHYTUNE			0x0c
35 #define REG_PHYCTL_A33			0x10
36 #define REG_PHY_OTGCTL			0x20
37 #define REG_PMU_UNK1			0x10
38 
39 /* Common Control Bits for Both PHYs */
40 #define PHY_PLL_BW			0x03
41 #define PHY_RES45_CAL_EN		0x0c
42 
43 /* Private Control Bits for Each PHY */
44 #define PHY_TX_AMPLITUDE_TUNE		0x20
45 #define PHY_TX_SLEWRATE_TUNE		0x22
46 #define PHY_DISCON_TH_SEL		0x2a
47 #define PHY_SQUELCH_DETECT		0x3c
48 
49 #define PHYCTL_DATA			BIT(7)
50 #define OTGCTL_ROUTE_MUSB		BIT(0)
51 
52 #define PHY_TX_RATE			BIT(4)
53 #define PHY_TX_MAGNITUDE		BIT(2)
54 #define PHY_TX_AMPLITUDE_LEN		5
55 
56 #define PHY_RES45_CAL_DATA		BIT(0)
57 #define PHY_RES45_CAL_LEN		1
58 #define PHY_DISCON_TH_LEN		2
59 
60 #define SUNXI_AHB_ICHR8_EN		BIT(10)
61 #define SUNXI_AHB_INCR4_BURST_EN	BIT(9)
62 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
63 #define SUNXI_ULPI_BYPASS_EN		BIT(0)
64 
65 /* A83T specific control bits for PHY0 */
66 #define PHY_CTL_VBUSVLDEXT		BIT(5)
67 #define PHY_CTL_SIDDQ			BIT(3)
68 
69 /* A83T specific control bits for PHY2 HSIC */
70 #define SUNXI_EHCI_HS_FORCE		BIT(20)
71 #define SUNXI_HSIC_CONNECT_INT		BIT(16)
72 #define SUNXI_HSIC			BIT(1)
73 
74 #define MAX_PHYS			4
75 
76 enum sun4i_usb_phy_type {
77 	sun4i_a10_phy,
78 	sun6i_a31_phy,
79 	sun8i_a33_phy,
80 	sun8i_a83t_phy,
81 	sun8i_h3_phy,
82 	sun8i_r40_phy,
83 	sun8i_v3s_phy,
84 	sun50i_a64_phy,
85 	sun50i_h6_phy,
86 };
87 
88 struct sun4i_usb_phy_cfg {
89 	int num_phys;
90 	enum sun4i_usb_phy_type type;
91 	u32 disc_thresh;
92 	u8 phyctl_offset;
93 	bool dedicated_clocks;
94 	bool enable_pmu_unk1;
95 	bool phy0_dual_route;
96 	int missing_phys;
97 };
98 
99 struct sun4i_usb_phy_info {
100 	const char *gpio_vbus;
101 	const char *gpio_vbus_det;
102 	const char *gpio_id_det;
103 } phy_info[] = {
104 	{
105 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
106 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
107 		.gpio_id_det = CONFIG_USB0_ID_DET,
108 	},
109 	{
110 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
111 		.gpio_vbus_det = NULL,
112 		.gpio_id_det = NULL,
113 	},
114 	{
115 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
116 		.gpio_vbus_det = NULL,
117 		.gpio_id_det = NULL,
118 	},
119 	{
120 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
121 		.gpio_vbus_det = NULL,
122 		.gpio_id_det = NULL,
123 	},
124 };
125 
126 struct sun4i_usb_phy_plat {
127 	void __iomem *pmu;
128 	int power_on_count;
129 	int gpio_vbus;
130 	int gpio_vbus_det;
131 	int gpio_id_det;
132 	struct clk clocks;
133 	struct reset_ctl resets;
134 	int id;
135 };
136 
137 struct sun4i_usb_phy_data {
138 	void __iomem *base;
139 	const struct sun4i_usb_phy_cfg *cfg;
140 	struct sun4i_usb_phy_plat *usb_phy;
141 	struct udevice *vbus_power_supply;
142 };
143 
144 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
145 
sun4i_usb_phy_write(struct phy * phy,u32 addr,u32 data,int len)146 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
147 {
148 	struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
149 	struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
150 	u32 temp, usbc_bit = BIT(usb_phy->id * 2);
151 	void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
152 	int i;
153 
154 	if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
155 		/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
156 		writel(0, phyctl);
157 	}
158 
159 	for (i = 0; i < len; i++) {
160 		temp = readl(phyctl);
161 
162 		/* clear the address portion */
163 		temp &= ~(0xff << 8);
164 
165 		/* set the address */
166 		temp |= ((addr + i) << 8);
167 		writel(temp, phyctl);
168 
169 		/* set the data bit and clear usbc bit*/
170 		temp = readb(phyctl);
171 		if (data & 0x1)
172 			temp |= PHYCTL_DATA;
173 		else
174 			temp &= ~PHYCTL_DATA;
175 		temp &= ~usbc_bit;
176 		writeb(temp, phyctl);
177 
178 		/* pulse usbc_bit */
179 		temp = readb(phyctl);
180 		temp |= usbc_bit;
181 		writeb(temp, phyctl);
182 
183 		temp = readb(phyctl);
184 		temp &= ~usbc_bit;
185 		writeb(temp, phyctl);
186 
187 		data >>= 1;
188 	}
189 }
190 
sun4i_usb_phy_passby(struct phy * phy,bool enable)191 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
192 {
193 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
194 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
195 	u32 bits, reg_value;
196 
197 	if (!usb_phy->pmu)
198 		return;
199 
200 	bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
201 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
202 
203 	/* A83T USB2 is HSIC */
204 	if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
205 		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
206 			SUNXI_HSIC;
207 
208 	reg_value = readl(usb_phy->pmu);
209 
210 	if (enable)
211 		reg_value |= bits;
212 	else
213 		reg_value &= ~bits;
214 
215 	writel(reg_value, usb_phy->pmu);
216 }
217 
sun4i_usb_phy_power_on(struct phy * phy)218 static int sun4i_usb_phy_power_on(struct phy *phy)
219 {
220 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
221 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
222 
223 	if (initial_usb_scan_delay) {
224 		mdelay(initial_usb_scan_delay);
225 		initial_usb_scan_delay = 0;
226 	}
227 
228 	usb_phy->power_on_count++;
229 	if (usb_phy->power_on_count != 1)
230 		return 0;
231 
232 	if (usb_phy->gpio_vbus >= 0)
233 		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
234 
235 	return 0;
236 }
237 
sun4i_usb_phy_power_off(struct phy * phy)238 static int sun4i_usb_phy_power_off(struct phy *phy)
239 {
240 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
241 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
242 
243 	usb_phy->power_on_count--;
244 	if (usb_phy->power_on_count != 0)
245 		return 0;
246 
247 	if (usb_phy->gpio_vbus >= 0)
248 		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
249 
250 	return 0;
251 }
252 
sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data * data,bool id_det)253 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
254 {
255 	u32 regval;
256 
257 	regval = readl(data->base + REG_PHY_OTGCTL);
258 	if (!id_det) {
259 		/* Host mode. Route phy0 to EHCI/OHCI */
260 		regval &= ~OTGCTL_ROUTE_MUSB;
261 	} else {
262 		/* Peripheral mode. Route phy0 to MUSB */
263 		regval |= OTGCTL_ROUTE_MUSB;
264 	}
265 	writel(regval, data->base + REG_PHY_OTGCTL);
266 }
267 
sun4i_usb_phy_init(struct phy * phy)268 static int sun4i_usb_phy_init(struct phy *phy)
269 {
270 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
271 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
272 	u32 val;
273 	int ret;
274 
275 	ret = clk_enable(&usb_phy->clocks);
276 	if (ret) {
277 		dev_err(phy->dev, "failed to enable usb_%ldphy clock\n",
278 			phy->id);
279 		return ret;
280 	}
281 
282 	ret = reset_deassert(&usb_phy->resets);
283 	if (ret) {
284 		dev_err(phy->dev, "failed to deassert usb_%ldreset reset\n",
285 			phy->id);
286 		return ret;
287 	}
288 
289 	if (data->cfg->type == sun8i_a83t_phy ||
290 	    data->cfg->type == sun50i_h6_phy) {
291 		if (phy->id == 0) {
292 			val = readl(data->base + data->cfg->phyctl_offset);
293 			val |= PHY_CTL_VBUSVLDEXT;
294 			val &= ~PHY_CTL_SIDDQ;
295 			writel(val, data->base + data->cfg->phyctl_offset);
296 		}
297 	} else {
298 		if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
299 			val = readl(usb_phy->pmu + REG_PMU_UNK1);
300 			writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
301 		}
302 
303 		if (usb_phy->id == 0)
304 			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
305 					    PHY_RES45_CAL_DATA,
306 					    PHY_RES45_CAL_LEN);
307 
308 		/* Adjust PHY's magnitude and rate */
309 		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
310 				    PHY_TX_MAGNITUDE | PHY_TX_RATE,
311 				    PHY_TX_AMPLITUDE_LEN);
312 
313 		/* Disconnect threshold adjustment */
314 		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
315 				    data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
316 	}
317 
318 #ifdef CONFIG_USB_MUSB_SUNXI
319 	/* Needed for HCI and conflicts with MUSB, keep PHY0 on MUSB */
320 	if (usb_phy->id != 0)
321 		sun4i_usb_phy_passby(phy, true);
322 
323 	/* Route PHY0 to MUSB to allow USB gadget */
324 	if (data->cfg->phy0_dual_route)
325 		sun4i_usb_phy0_reroute(data, true);
326 #else
327 	sun4i_usb_phy_passby(phy, true);
328 
329 	/* Route PHY0 to HCI to allow USB host */
330 	if (data->cfg->phy0_dual_route)
331 		sun4i_usb_phy0_reroute(data, false);
332 #endif
333 
334 	return 0;
335 }
336 
sun4i_usb_phy_exit(struct phy * phy)337 static int sun4i_usb_phy_exit(struct phy *phy)
338 {
339 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
340 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
341 	int ret;
342 
343 	if (phy->id == 0) {
344 		if (data->cfg->type == sun8i_a83t_phy ||
345 		    data->cfg->type == sun50i_h6_phy) {
346 			void __iomem *phyctl = data->base +
347 				data->cfg->phyctl_offset;
348 
349 			writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
350 		}
351 	}
352 
353 	sun4i_usb_phy_passby(phy, false);
354 
355 	ret = clk_disable(&usb_phy->clocks);
356 	if (ret) {
357 		dev_err(phy->dev, "failed to disable usb_%ldphy clock\n",
358 			phy->id);
359 		return ret;
360 	}
361 
362 	ret = reset_assert(&usb_phy->resets);
363 	if (ret) {
364 		dev_err(phy->dev, "failed to assert usb_%ldreset reset\n",
365 			phy->id);
366 		return ret;
367 	}
368 
369 	return 0;
370 }
371 
sun4i_usb_phy_xlate(struct phy * phy,struct ofnode_phandle_args * args)372 static int sun4i_usb_phy_xlate(struct phy *phy,
373 			       struct ofnode_phandle_args *args)
374 {
375 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
376 
377 	if (args->args_count >= data->cfg->num_phys)
378 		return -EINVAL;
379 
380 	if (data->cfg->missing_phys & BIT(args->args[0]))
381 		return -ENODEV;
382 
383 	if (args->args_count)
384 		phy->id = args->args[0];
385 	else
386 		phy->id = 0;
387 
388 	debug("%s: phy_id = %ld\n", __func__, phy->id);
389 	return 0;
390 }
391 
sun4i_usb_phy_vbus_detect(struct phy * phy)392 int sun4i_usb_phy_vbus_detect(struct phy *phy)
393 {
394 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
395 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
396 	int err = 1, retries = 3;
397 
398 	if (usb_phy->gpio_vbus_det >= 0) {
399 		err = gpio_get_value(usb_phy->gpio_vbus_det);
400 		/*
401 		 * Vbus may have been provided by the board and just turned off
402 		 * some milliseconds ago on reset. What we're measuring then is
403 		 * a residual charge on Vbus. Sleep a bit and try again.
404 		 */
405 		while (err > 0 && retries--) {
406 			mdelay(100);
407 			err = gpio_get_value(usb_phy->gpio_vbus_det);
408 		}
409 	} else if (data->vbus_power_supply) {
410 		err = regulator_get_enable(data->vbus_power_supply);
411 	}
412 
413 	return err;
414 }
415 
sun4i_usb_phy_id_detect(struct phy * phy)416 int sun4i_usb_phy_id_detect(struct phy *phy)
417 {
418 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
419 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
420 
421 	if (usb_phy->gpio_id_det < 0)
422 		return usb_phy->gpio_id_det;
423 
424 	return gpio_get_value(usb_phy->gpio_id_det);
425 }
426 
sun4i_usb_phy_set_squelch_detect(struct phy * phy,bool enabled)427 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
428 {
429 	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
430 }
431 
432 static struct phy_ops sun4i_usb_phy_ops = {
433 	.of_xlate = sun4i_usb_phy_xlate,
434 	.init = sun4i_usb_phy_init,
435 	.power_on = sun4i_usb_phy_power_on,
436 	.power_off = sun4i_usb_phy_power_off,
437 	.exit = sun4i_usb_phy_exit,
438 };
439 
sun4i_usb_phy_probe(struct udevice * dev)440 static int sun4i_usb_phy_probe(struct udevice *dev)
441 {
442 	struct sun4i_usb_phy_plat *plat = dev_get_plat(dev);
443 	struct sun4i_usb_phy_data *data = dev_get_priv(dev);
444 	int i, ret;
445 
446 	data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
447 	if (!data->cfg)
448 		return -EINVAL;
449 
450 	data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
451 	if (IS_ERR(data->base))
452 		return PTR_ERR(data->base);
453 
454 	device_get_supply_regulator(dev, "usb0_vbus_power-supply",
455 				    &data->vbus_power_supply);
456 
457 	data->usb_phy = plat;
458 	for (i = 0; i < data->cfg->num_phys; i++) {
459 		struct sun4i_usb_phy_plat *phy = &plat[i];
460 		struct sun4i_usb_phy_info *info = &phy_info[i];
461 		char name[16];
462 
463 		if (data->cfg->missing_phys & BIT(i))
464 			continue;
465 
466 		phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
467 		if (phy->gpio_vbus >= 0) {
468 			ret = gpio_request(phy->gpio_vbus, "usb_vbus");
469 			if (ret)
470 				return ret;
471 			ret = gpio_direction_output(phy->gpio_vbus, 0);
472 			if (ret)
473 				return ret;
474 		}
475 
476 		phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
477 		if (phy->gpio_vbus_det >= 0) {
478 			ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
479 			if (ret)
480 				return ret;
481 			ret = gpio_direction_input(phy->gpio_vbus_det);
482 			if (ret)
483 				return ret;
484 		}
485 
486 		phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
487 		if (phy->gpio_id_det >= 0) {
488 			ret = gpio_request(phy->gpio_id_det, "usb_id_det");
489 			if (ret)
490 				return ret;
491 			ret = gpio_direction_input(phy->gpio_id_det);
492 			if (ret)
493 				return ret;
494 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
495 		}
496 
497 		if (data->cfg->dedicated_clocks)
498 			snprintf(name, sizeof(name), "usb%d_phy", i);
499 		else
500 			strlcpy(name, "usb_phy", sizeof(name));
501 
502 		ret = clk_get_by_name(dev, name, &phy->clocks);
503 		if (ret) {
504 			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
505 			return ret;
506 		}
507 
508 		snprintf(name, sizeof(name), "usb%d_reset", i);
509 		ret = reset_get_by_name(dev, name, &phy->resets);
510 		if (ret) {
511 			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
512 			return ret;
513 		}
514 
515 		if (i || data->cfg->phy0_dual_route) {
516 			snprintf(name, sizeof(name), "pmu%d", i);
517 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
518 			if (IS_ERR(phy->pmu))
519 				return PTR_ERR(phy->pmu);
520 		}
521 
522 		phy->id = i;
523 	};
524 
525 	debug("Allwinner Sun4I USB PHY driver loaded\n");
526 	return 0;
527 }
528 
529 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
530 	.num_phys = 3,
531 	.type = sun4i_a10_phy,
532 	.disc_thresh = 3,
533 	.phyctl_offset = REG_PHYCTL_A10,
534 	.dedicated_clocks = false,
535 	.enable_pmu_unk1 = false,
536 };
537 
538 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
539 	.num_phys = 2,
540 	.type = sun4i_a10_phy,
541 	.disc_thresh = 2,
542 	.phyctl_offset = REG_PHYCTL_A10,
543 	.dedicated_clocks = false,
544 	.enable_pmu_unk1 = false,
545 };
546 
547 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
548 	.num_phys = 3,
549 	.type = sun6i_a31_phy,
550 	.disc_thresh = 3,
551 	.phyctl_offset = REG_PHYCTL_A10,
552 	.dedicated_clocks = true,
553 	.enable_pmu_unk1 = false,
554 };
555 
556 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
557 	.num_phys = 3,
558 	.type = sun4i_a10_phy,
559 	.disc_thresh = 2,
560 	.phyctl_offset = REG_PHYCTL_A10,
561 	.dedicated_clocks = false,
562 	.enable_pmu_unk1 = false,
563 };
564 
565 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
566 	.num_phys = 2,
567 	.type = sun4i_a10_phy,
568 	.disc_thresh = 3,
569 	.phyctl_offset = REG_PHYCTL_A10,
570 	.dedicated_clocks = true,
571 	.enable_pmu_unk1 = false,
572 };
573 
574 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
575 	.num_phys = 2,
576 	.type = sun8i_a33_phy,
577 	.disc_thresh = 3,
578 	.phyctl_offset = REG_PHYCTL_A33,
579 	.dedicated_clocks = true,
580 	.enable_pmu_unk1 = false,
581 };
582 
583 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
584 	.num_phys = 3,
585 	.type = sun8i_a83t_phy,
586 	.phyctl_offset = REG_PHYCTL_A33,
587 	.dedicated_clocks = true,
588 };
589 
590 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
591 	.num_phys = 4,
592 	.type = sun8i_h3_phy,
593 	.disc_thresh = 3,
594 	.phyctl_offset = REG_PHYCTL_A33,
595 	.dedicated_clocks = true,
596 	.enable_pmu_unk1 = true,
597 	.phy0_dual_route = true,
598 };
599 
600 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
601 	.num_phys = 3,
602 	.type = sun8i_r40_phy,
603 	.disc_thresh = 3,
604 	.phyctl_offset = REG_PHYCTL_A33,
605 	.dedicated_clocks = true,
606 	.enable_pmu_unk1 = true,
607 	.phy0_dual_route = true,
608 };
609 
610 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
611 	.num_phys = 1,
612 	.type = sun8i_v3s_phy,
613 	.disc_thresh = 3,
614 	.phyctl_offset = REG_PHYCTL_A33,
615 	.dedicated_clocks = true,
616 	.enable_pmu_unk1 = true,
617 	.phy0_dual_route = true,
618 };
619 
620 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
621 	.num_phys = 2,
622 	.type = sun50i_a64_phy,
623 	.disc_thresh = 3,
624 	.phyctl_offset = REG_PHYCTL_A33,
625 	.dedicated_clocks = true,
626 	.enable_pmu_unk1 = true,
627 	.phy0_dual_route = true,
628 };
629 
630 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
631 	.num_phys = 4,
632 	.type = sun50i_h6_phy,
633 	.disc_thresh = 3,
634 	.phyctl_offset = REG_PHYCTL_A33,
635 	.dedicated_clocks = true,
636 	.enable_pmu_unk1 = true,
637 	.phy0_dual_route = true,
638 	.missing_phys = BIT(1) | BIT(2),
639 };
640 
641 static const struct udevice_id sun4i_usb_phy_ids[] = {
642 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
643 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
644 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
645 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
646 	{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
647 	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
648 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
649 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
650 	{ .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
651 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
652 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
653 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
654 	{ }
655 };
656 
657 U_BOOT_DRIVER(sun4i_usb_phy) = {
658 	.name	= "sun4i_usb_phy",
659 	.id	= UCLASS_PHY,
660 	.of_match = sun4i_usb_phy_ids,
661 	.ops = &sun4i_usb_phy_ops,
662 	.probe = sun4i_usb_phy_probe,
663 	.plat_auto	= sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
664 	.priv_auto	= sizeof(struct sun4i_usb_phy_data),
665 };
666