1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Marvell International Ltd.
4 */
5
6 #include <common.h>
7 #include <fdtdec.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <linux/delay.h>
14
15 #include "comphy_a3700.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct comphy_mux_data a3700_comphy_mux_data[] = {
20 /* Lane 0 */
21 {
22 4,
23 {
24 { COMPHY_TYPE_UNCONNECTED, 0x0 },
25 { COMPHY_TYPE_SGMII1, 0x0 },
26 { COMPHY_TYPE_USB3_HOST0, 0x1 },
27 { COMPHY_TYPE_USB3_DEVICE, 0x1 }
28 }
29 },
30 /* Lane 1 */
31 {
32 3,
33 {
34 { COMPHY_TYPE_UNCONNECTED, 0x0},
35 { COMPHY_TYPE_SGMII0, 0x0},
36 { COMPHY_TYPE_PEX0, 0x1}
37 }
38 },
39 /* Lane 2 */
40 {
41 4,
42 {
43 { COMPHY_TYPE_UNCONNECTED, 0x0},
44 { COMPHY_TYPE_SATA0, 0x0},
45 { COMPHY_TYPE_USB3_HOST0, 0x1},
46 { COMPHY_TYPE_USB3_DEVICE, 0x1}
47 }
48 },
49 };
50
51 struct sgmii_phy_init_data_fix {
52 u16 addr;
53 u16 value;
54 };
55
56 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
57 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
58 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
59 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
60 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
61 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
62 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
63 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
64 {0x104, 0x0C10}
65 };
66
67 /* 40M1G25 mode init data */
68 static u16 sgmii_phy_init[512] = {
69 /* 0 1 2 3 4 5 6 7 */
70 /*-----------------------------------------------------------*/
71 /* 8 9 A B C D E F */
72 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
73 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
74 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
75 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
76 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
77 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
78 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
79 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
80 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
81 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
82 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
83 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
84 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
85 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
86 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
87 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
88 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
89 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
90 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
91 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
92 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
93 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
95 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
96 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
97 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
98 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
99 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
100 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
101 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
102 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
103 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
104 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
106 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
119 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
133 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
134 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
135 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
136 };
137
138 /*
139 * comphy_poll_reg
140 *
141 * return: 1 on success, 0 on timeout
142 */
comphy_poll_reg(void * addr,u32 val,u32 mask,u8 op_type)143 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
144 {
145 u32 rval = 0xDEAD, timeout;
146
147 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
148 if (op_type == POLL_16B_REG)
149 rval = readw(addr); /* 16 bit */
150 else
151 rval = readl(addr) ; /* 32 bit */
152
153 if ((rval & mask) == val)
154 return 1;
155
156 udelay(10000);
157 }
158
159 debug("Time out waiting (%p = %#010x)\n", addr, rval);
160 return 0;
161 }
162
163 /*
164 * comphy_pcie_power_up
165 *
166 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
167 */
comphy_pcie_power_up(u32 speed,u32 invert)168 static int comphy_pcie_power_up(u32 speed, u32 invert)
169 {
170 int ret;
171
172 debug_enter();
173
174 /*
175 * 1. Enable max PLL.
176 */
177 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
178
179 /*
180 * 2. Select 20 bit SERDES interface.
181 */
182 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
183
184 /*
185 * 3. Force to use reg setting for PCIe mode
186 */
187 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
188
189 /*
190 * 4. Change RX wait
191 */
192 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
193
194 /*
195 * 5. Enable idle sync
196 */
197 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
198
199 /*
200 * 6. Enable the output of 100M/125M/500M clock
201 */
202 reg_set16(phy_addr(PCIE, MISC_REG0),
203 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
204
205 /*
206 * 7. Enable TX
207 */
208 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
209
210 /*
211 * 8. Check crystal jumper setting and program the Power and PLL
212 * Control accordingly
213 */
214 if (get_ref_clk() == 40) {
215 /* 40 MHz */
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
217 } else {
218 /* 25 MHz */
219 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
220 }
221
222 /*
223 * 9. Override Speed_PLL value and use MAC PLL
224 */
225 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
226 0xFFFF);
227
228 /*
229 * 10. Check the Polarity invert bit
230 */
231 if (invert & COMPHY_POLARITY_TXD_INVERT)
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
233 else
234 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
235
236 if (invert & COMPHY_POLARITY_RXD_INVERT)
237 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
238 else
239 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
240
241 /*
242 * 11. Release SW reset
243 */
244 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
245 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
246 bf_soft_rst | bf_mode_refdiv);
247
248 /* Wait for > 55 us to allow PCLK be enabled */
249 udelay(PLL_SET_DELAY_US);
250
251 /* Assert PCLK enabled */
252 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
253 rb_txdclk_pclk_en, /* value */
254 rb_txdclk_pclk_en, /* mask */
255 POLL_16B_REG); /* 16bit */
256 if (!ret)
257 printf("Failed to lock PCIe PLL\n");
258
259 debug_exit();
260
261 /* Return the status of the PLL */
262 return ret;
263 }
264
265 /*
266 * reg_set_indirect
267 *
268 * return: void
269 */
reg_set_indirect(u32 reg,u16 data,u16 mask)270 static void reg_set_indirect(u32 reg, u16 data, u16 mask)
271 {
272 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF);
273 reg_set(rh_vsreg_data, data, mask);
274 }
275
276 /*
277 * comphy_sata_power_up
278 *
279 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
280 */
comphy_sata_power_up(u32 invert)281 static int comphy_sata_power_up(u32 invert)
282 {
283 int ret;
284 u32 data = 0;
285
286 debug_enter();
287
288 /*
289 * 0. Check the Polarity invert bits
290 */
291 if (invert & COMPHY_POLARITY_TXD_INVERT)
292 data |= bs_txd_inv;
293
294 if (invert & COMPHY_POLARITY_RXD_INVERT)
295 data |= bs_rxd_inv;
296
297 reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
298
299 /*
300 * 1. Select 40-bit data width width
301 */
302 reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
303
304 /*
305 * 2. Select reference clock and PHY mode (SATA)
306 */
307 if (get_ref_clk() == 40) {
308 /* 40 MHz */
309 reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
310 } else {
311 /* 20 MHz */
312 reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
313 }
314
315 /*
316 * 3. Use maximum PLL rate (no power save)
317 */
318 reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
319
320 /*
321 * 4. Reset reserved bit (??)
322 */
323 reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
324
325 /*
326 * 5. Set vendor-specific configuration (??)
327 */
328 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
329 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
330
331 /* Wait for > 55 us to allow PLL be enabled */
332 udelay(PLL_SET_DELAY_US);
333
334 /* Assert SATA PLL enabled */
335 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
336 ret = comphy_poll_reg(rh_vsreg_data, /* address */
337 bs_pll_ready_tx, /* value */
338 bs_pll_ready_tx, /* mask */
339 POLL_32B_REG); /* 32bit */
340 if (!ret)
341 printf("Failed to lock SATA PLL\n");
342
343 debug_exit();
344
345 return ret;
346 }
347
348 /*
349 * usb3_reg_set16
350 *
351 * return: void
352 */
usb3_reg_set16(u32 reg,u16 data,u16 mask,u32 lane)353 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)
354 {
355 /*
356 * When Lane 2 PHY is for USB3, access the PHY registers
357 * through indirect Address and Data registers INDIR_ACC_PHY_ADDR
358 * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
359 * within the SATA Host Controller registers, Lane 2 base register
360 * offset is 0x200
361 */
362
363 if (lane == 2)
364 reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,
365 mask);
366 else
367 reg_set16(phy_addr(USB3, reg), data, mask);
368 }
369
370 /*
371 * comphy_usb3_power_up
372 *
373 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
374 */
comphy_usb3_power_up(u32 lane,u32 type,u32 speed,u32 invert)375 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
376 {
377 int ret;
378
379 debug_enter();
380
381 /*
382 * 1. Power up OTG module
383 */
384 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
385
386 /*
387 * 2. Set counter for 100us pulse in USB3 Host and Device
388 * restore default burst size limit (Reference Clock 31:24)
389 */
390 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns);
391
392
393 /* 0xd005c300 = 0x1001 */
394 /* set PRD_TXDEEMPH (3.5db de-emph) */
395 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
396
397 /*
398 * Set BIT0: enable transmitter in high impedance mode
399 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
400 * Set BIT6: Tx detect Rx at HiZ mode
401 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
402 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
403 * register
404 */
405 usb3_reg_set16(LANE_CFG1,
406 tx_det_rx_mode | gen2_tx_data_dly_deft
407 | tx_elec_idle_mode_en,
408 prd_txdeemph1_mask | tx_det_rx_mode
409 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);
410
411 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
412 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
413
414 /*
415 * set Override Margining Controls From the MAC: Use margining signals
416 * from lane configuration
417 */
418 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);
419
420 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
421 /* set Mode Clock Source = PCLK is generated from REFCLK */
422 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);
423
424 /* set G2 Spread Spectrum Clock Amplitude at 4K */
425 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);
426
427 /*
428 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
429 * Master Current Select
430 */
431 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);
432
433 /*
434 * 3. Check crystal jumper setting and program the Power and PLL
435 * Control accordingly
436 * 4. Change RX wait
437 */
438 if (get_ref_clk() == 40) {
439 /* 40 MHz */
440 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
441 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
442 } else {
443 /* 25 MHz */
444 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
445 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
446 }
447
448 /*
449 * 5. Enable idle sync
450 */
451 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);
452
453 /*
454 * 6. Enable the output of 500M clock
455 */
456 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);
457
458 /*
459 * 7. Set 20-bit data width
460 */
461 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);
462
463 /*
464 * 8. Override Speed_PLL value and use MAC PLL
465 */
466 usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF,
467 lane);
468
469 /*
470 * 9. Check the Polarity invert bit
471 */
472 if (invert & COMPHY_POLARITY_TXD_INVERT)
473 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
474 else
475 usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
476
477 if (invert & COMPHY_POLARITY_RXD_INVERT)
478 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
479 else
480 usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
481
482 /*
483 * 10. Set max speed generation to USB3.0 5Gbps
484 */
485 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);
486
487 /*
488 * 11. Set capacitor value for FFE gain peaking to 0xF
489 */
490 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);
491
492 /*
493 * 12. Release SW reset
494 */
495 usb3_reg_set16(GLOB_PHY_CTRL0,
496 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
497 | 0x20, 0xFFFF, lane);
498
499 /* Wait for > 55 us to allow PCLK be enabled */
500 udelay(PLL_SET_DELAY_US);
501
502 /* Assert PCLK enabled */
503 if (lane == 2) {
504 reg_set(rh_vsreg_addr,
505 LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET,
506 0xFFFFFFFF);
507 ret = comphy_poll_reg(rh_vsreg_data, /* address */
508 rb_txdclk_pclk_en, /* value */
509 rb_txdclk_pclk_en, /* mask */
510 POLL_32B_REG); /* 32bit */
511 } else {
512 ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
513 rb_txdclk_pclk_en, /* value */
514 rb_txdclk_pclk_en, /* mask */
515 POLL_16B_REG); /* 16bit */
516 }
517 if (!ret)
518 printf("Failed to lock USB3 PLL\n");
519
520 /*
521 * Set Soft ID for Host mode (Device mode works with Hard ID
522 * detection)
523 */
524 if (type == COMPHY_TYPE_USB3_HOST0) {
525 /*
526 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
527 * clear BIT1: set SOFT_ID = Host
528 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
529 * interrupt by ID instead of using both interrupts
530 * of HOST and Device ORed simultaneously
531 * INT_MODE=ID in order to avoid unexpected
532 * behaviour or both interrupts together
533 */
534 reg_set(USB32_CTRL_BASE,
535 usb32_ctrl_id_mode | usb32_ctrl_int_mode,
536 usb32_ctrl_id_mode | usb32_ctrl_soft_id |
537 usb32_ctrl_int_mode);
538 }
539
540 debug_exit();
541
542 return ret;
543 }
544
545 /*
546 * comphy_usb2_power_up
547 *
548 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
549 */
comphy_usb2_power_up(u8 usb32)550 static int comphy_usb2_power_up(u8 usb32)
551 {
552 int ret;
553
554 debug_enter();
555
556 if (usb32 != 0 && usb32 != 1) {
557 printf("invalid usb32 value: (%d), should be either 0 or 1\n",
558 usb32);
559 debug_exit();
560 return 0;
561 }
562
563 /*
564 * 0. Setup PLL. 40MHz clock uses defaults.
565 * See "PLL Settings for Typical REFCLK" table
566 */
567 if (get_ref_clk() == 25) {
568 reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16),
569 0x3F | (0xFF << 16) | (0x3 << 28));
570 }
571
572 /*
573 * 1. PHY pull up and disable USB2 suspend
574 */
575 reg_set(USB2_PHY_CTRL_ADDR(usb32),
576 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
577
578 if (usb32 != 0) {
579 /*
580 * 2. Power up OTG module
581 */
582 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
583
584 /*
585 * 3. Configure PHY charger detection
586 */
587 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0,
588 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
589 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
590 }
591
592 /* Assert PLL calibration done */
593 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
594 rb_usb2phy_pllcal_done, /* value */
595 rb_usb2phy_pllcal_done, /* mask */
596 POLL_32B_REG); /* 32bit */
597 if (!ret) {
598 printf("Failed to end USB2 PLL calibration\n");
599 goto out;
600 }
601
602 /* Assert impedance calibration done */
603 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
604 rb_usb2phy_impcal_done, /* value */
605 rb_usb2phy_impcal_done, /* mask */
606 POLL_32B_REG); /* 32bit */
607 if (!ret) {
608 printf("Failed to end USB2 impedance calibration\n");
609 goto out;
610 }
611
612 /* Assert squetch calibration done */
613 ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
614 rb_usb2phy_sqcal_done, /* value */
615 rb_usb2phy_sqcal_done, /* mask */
616 POLL_32B_REG); /* 32bit */
617 if (!ret) {
618 printf("Failed to end USB2 unknown calibration\n");
619 goto out;
620 }
621
622 /* Assert PLL is ready */
623 ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
624 rb_usb2phy_pll_ready, /* value */
625 rb_usb2phy_pll_ready, /* mask */
626 POLL_32B_REG); /* 32bit */
627
628 if (!ret) {
629 printf("Failed to lock USB2 PLL\n");
630 goto out;
631 }
632
633 out:
634 debug_exit();
635
636 return ret;
637 }
638
639 /*
640 * comphy_emmc_power_up
641 *
642 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
643 */
comphy_emmc_power_up(void)644 static int comphy_emmc_power_up(void)
645 {
646 debug_enter();
647
648 /*
649 * 1. Bus power ON, Bus voltage 1.8V
650 */
651 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
652
653 /*
654 * 2. Set FIFO parameters
655 */
656 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
657
658 /*
659 * 3. Set Capabilities 1_2
660 */
661 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
662
663 /*
664 * 4. Set Endian
665 */
666 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0);
667
668 /*
669 * 4. Init PHY
670 */
671 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
672 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000);
673
674 /*
675 * 5. DLL reset
676 */
677 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
678 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0);
679
680 debug_exit();
681
682 return 1;
683 }
684
685 /*
686 * comphy_sgmii_power_up
687 *
688 * return:
689 */
comphy_sgmii_phy_init(u32 lane,u32 speed)690 static void comphy_sgmii_phy_init(u32 lane, u32 speed)
691 {
692 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
693 int addr, fix_idx;
694 u16 val;
695
696 fix_idx = 0;
697 for (addr = 0; addr < 512; addr++) {
698 /*
699 * All PHY register values are defined in full for 3.125Gbps
700 * SERDES speed. The values required for 1.25 Gbps are almost
701 * the same and only few registers should be "fixed" in
702 * comparison to 3.125 Gbps values. These register values are
703 * stored in "sgmii_phy_init_fix" array.
704 */
705 if (speed != COMPHY_SPEED_1_25G &&
706 sgmii_phy_init_fix[fix_idx].addr == addr) {
707 /* Use new value */
708 val = sgmii_phy_init_fix[fix_idx].value;
709 if (fix_idx < fix_arr_sz)
710 fix_idx++;
711 } else {
712 val = sgmii_phy_init[addr];
713 }
714
715 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
716 }
717 }
718
719 /*
720 * comphy_sgmii_power_up
721 *
722 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
723 */
comphy_sgmii_power_up(u32 lane,u32 speed,u32 invert)724 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
725 {
726 int ret;
727 u32 saved_selector;
728
729 debug_enter();
730
731 /*
732 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
733 */
734 saved_selector = readl(COMPHY_SEL_ADDR);
735 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
736
737 /*
738 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
739 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
740 * PHY TXP/TXN output to idle state during PHY initialization
741 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
742 */
743 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
744 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
745 rb_pin_reset_core | rb_pin_pu_pll |
746 rb_pin_pu_rx | rb_pin_pu_tx);
747
748 /*
749 * 5. Release reset to the PHY by setting PIN_RESET=0.
750 */
751 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy);
752
753 /*
754 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
755 * COMPHY bit rate
756 */
757 if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
758 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
759 (0x8 << rf_gen_rx_sel_shift) |
760 (0x8 << rf_gen_tx_sel_shift),
761 rf_gen_rx_select | rf_gen_tx_select);
762
763 } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
764 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
765 (0x6 << rf_gen_rx_sel_shift) |
766 (0x6 << rf_gen_tx_sel_shift),
767 rf_gen_rx_select | rf_gen_tx_select);
768 } else {
769 printf("Unsupported COMPHY speed!\n");
770 return 0;
771 }
772
773 /*
774 * 8. Wait 1mS for bandgap and reference clocks to stabilize;
775 * then start SW programming.
776 */
777 mdelay(10);
778
779 /* 9. Program COMPHY register PHY_MODE */
780 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
781 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
782
783 /*
784 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
785 * source
786 */
787 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);
788
789 /*
790 * 11. Set correct reference clock frequency in COMPHY register
791 * REF_FREF_SEL.
792 */
793 if (get_ref_clk() == 40) {
794 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
795 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
796 } else {
797 /* 25MHz */
798 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
799 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
800 }
801
802 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
803 /*
804 * This step is mentioned in the flow received from verification team.
805 * However the PHY_GEN_MAX value is only meaningful for other
806 * interfaces (not SGMII). For instance, it selects SATA speed
807 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
808 */
809
810 /*
811 * 13. Program COMPHY register SEL_BITS to set correct parallel data
812 * bus width
813 */
814 /* 10bit */
815 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);
816
817 /*
818 * 14. As long as DFE function needs to be enabled in any mode,
819 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
820 * for real chip during COMPHY power on.
821 */
822 /*
823 * The step 14 exists (and empty) in the original initialization flow
824 * obtained from the verification team. According to the functional
825 * specification DFE_UPDATE_EN already has the default value 0x3F
826 */
827
828 /*
829 * 15. Program COMPHY GEN registers.
830 * These registers should be programmed based on the lab testing
831 * result to achieve optimal performance. Please contact the CEA
832 * group to get the related GEN table during real chip bring-up.
833 * We only requred to run though the entire registers programming
834 * flow defined by "comphy_sgmii_phy_init" when the REF clock is
835 * 40 MHz. For REF clock 25 MHz the default values stored in PHY
836 * registers are OK.
837 */
838 debug("Running C-DPI phy init %s mode\n",
839 speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
840 if (get_ref_clk() == 40)
841 comphy_sgmii_phy_init(lane, speed);
842
843 /*
844 * 16. [Simulation Only] should not be used for real chip.
845 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
846 * (R02h[9]) to 1 to shorten COMPHY simulation time.
847 */
848 /*
849 * 17. [Simulation Only: should not be used for real chip]
850 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
851 * training simulation time.
852 */
853
854 /*
855 * 18. Check the PHY Polarity invert bit
856 */
857 if (invert & COMPHY_POLARITY_TXD_INVERT)
858 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
859 else
860 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
861
862 if (invert & COMPHY_POLARITY_RXD_INVERT)
863 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
864 else
865 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
866
867 /*
868 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
869 * to start PHY power up sequence. All the PHY register
870 * programming should be done before PIN_PU_PLL=1. There should be
871 * no register programming for normal PHY operation from this point.
872 */
873 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
874 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
875 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
876
877 /*
878 * 20. Wait for PHY power up sequence to finish by checking output ports
879 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
880 */
881 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
882 rb_pll_ready_tx | rb_pll_ready_rx, /* value */
883 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
884 POLL_32B_REG); /* 32bit */
885 if (!ret) {
886 printf("Failed to lock PLL for SGMII PHY %d\n", lane);
887 goto out;
888 }
889
890 /*
891 * 21. Set COMPHY input port PIN_TX_IDLE=0
892 */
893 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle);
894
895 /*
896 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
897 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
898 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
899 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
900 * PIN_RX_INIT_DONE= 1.
901 * Please refer to RX initialization part for details.
902 */
903 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0);
904
905 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
906 rb_rx_init_done, /* value */
907 rb_rx_init_done, /* mask */
908 POLL_32B_REG); /* 32bit */
909 if (!ret) {
910 printf("Failed to init RX of SGMII PHY %d\n", lane);
911 goto out;
912 }
913
914 /*
915 * Restore saved selector.
916 */
917 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
918
919 out:
920 debug_exit();
921
922 return ret;
923 }
924
comphy_dedicated_phys_init(void)925 void comphy_dedicated_phys_init(void)
926 {
927 int node, usb32, ret = 1;
928 const void *blob = gd->fdt_blob;
929
930 debug_enter();
931
932 for (usb32 = 0; usb32 <= 1; usb32++) {
933 /*
934 * There are 2 UTMI PHYs in this SOC.
935 * One is independendent and one is paired with USB3 port (OTG)
936 */
937 if (usb32 == 0) {
938 node = fdt_node_offset_by_compatible(
939 blob, -1, "marvell,armada3700-ehci");
940 } else {
941 node = fdt_node_offset_by_compatible(
942 blob, -1, "marvell,armada3700-xhci");
943 }
944
945 if (node > 0) {
946 if (fdtdec_get_is_enabled(blob, node)) {
947 ret = comphy_usb2_power_up(usb32);
948 if (!ret)
949 printf("Failed to initialize UTMI PHY\n");
950 else
951 debug("UTMI PHY init succeed\n");
952 } else {
953 debug("USB%d node is disabled\n",
954 usb32 == 0 ? 2 : 3);
955 }
956 } else {
957 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
958 }
959 }
960
961 node = fdt_node_offset_by_compatible(blob, -1,
962 "marvell,armada-8k-sdhci");
963 if (node <= 0) {
964 node = fdt_node_offset_by_compatible(
965 blob, -1, "marvell,armada-3700-sdhci");
966 }
967
968 if (node > 0) {
969 if (fdtdec_get_is_enabled(blob, node)) {
970 ret = comphy_emmc_power_up();
971 if (!ret)
972 printf("Failed to initialize SDIO/eMMC PHY\n");
973 else
974 debug("SDIO/eMMC PHY init succeed\n");
975 } else {
976 debug("SDIO/eMMC node is disabled\n");
977 }
978 } else {
979 debug("No SDIO/eMMC node in DT\n");
980 }
981
982 debug_exit();
983 }
984
comphy_a3700_init(struct chip_serdes_phy_config * chip_cfg,struct comphy_map * serdes_map)985 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
986 struct comphy_map *serdes_map)
987 {
988 struct comphy_map *comphy_map;
989 u32 comphy_max_count = chip_cfg->comphy_lanes_count;
990 u32 lane, ret = 0;
991
992 debug_enter();
993
994 /* Initialize PHY mux */
995 chip_cfg->mux_data = a3700_comphy_mux_data;
996 comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
997
998 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
999 lane++, comphy_map++) {
1000 debug("Initialize serdes number %d\n", lane);
1001 debug("Serdes type = 0x%x invert=%d\n",
1002 comphy_map->type, comphy_map->invert);
1003
1004 switch (comphy_map->type) {
1005 case COMPHY_TYPE_UNCONNECTED:
1006 continue;
1007 break;
1008
1009 case COMPHY_TYPE_PEX0:
1010 ret = comphy_pcie_power_up(comphy_map->speed,
1011 comphy_map->invert);
1012 break;
1013
1014 case COMPHY_TYPE_USB3_HOST0:
1015 case COMPHY_TYPE_USB3_DEVICE:
1016 ret = comphy_usb3_power_up(lane,
1017 comphy_map->type,
1018 comphy_map->speed,
1019 comphy_map->invert);
1020 break;
1021
1022 case COMPHY_TYPE_SGMII0:
1023 case COMPHY_TYPE_SGMII1:
1024 ret = comphy_sgmii_power_up(lane, comphy_map->speed,
1025 comphy_map->invert);
1026 break;
1027
1028 case COMPHY_TYPE_SATA0:
1029 ret = comphy_sata_power_up(comphy_map->invert);
1030 break;
1031
1032 default:
1033 debug("Unknown SerDes type, skip initialize SerDes %d\n",
1034 lane);
1035 ret = 1;
1036 break;
1037 }
1038 if (!ret)
1039 printf("PLL is not locked - Failed to initialize lane %d\n",
1040 lane);
1041 }
1042
1043 debug_exit();
1044 return ret;
1045 }
1046