1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <dm/pinctrl.h>
13 #include <mach/ar71xx_regs.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 enum periph_id {
18 PERIPH_ID_UART0,
19 PERIPH_ID_SPI0,
20 PERIPH_ID_NONE = -1,
21 };
22
23 struct qca953x_pinctrl_priv {
24 void __iomem *regs;
25 };
26
pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv * priv,int cs)27 static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
28 {
29 switch (cs) {
30 case 0:
31 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
32 QCA953X_GPIO(5) | QCA953X_GPIO(6) |
33 QCA953X_GPIO(7), QCA953X_GPIO(8));
34
35 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
36 QCA953X_GPIO_MUX_MASK(8) |
37 QCA953X_GPIO_MUX_MASK(16) |
38 QCA953X_GPIO_MUX_MASK(24),
39 (QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
40 (QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
41 (QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
42
43 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
44 QCA953X_GPIO_MUX_MASK(0),
45 QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
46
47 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
48 QCA953X_GPIO(8));
49 break;
50 }
51 }
52
pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv * priv,int uart_id)53 static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
54 {
55 switch (uart_id) {
56 case PERIPH_ID_UART0:
57 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
58 QCA953X_GPIO(9), QCA953X_GPIO(10));
59
60 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
61 QCA953X_GPIO_MUX_MASK(16),
62 QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
63
64 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
65 QCA953X_GPIO_MUX_MASK(8),
66 QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
67
68 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
69 QCA953X_GPIO(10));
70 break;
71 }
72 }
73
qca953x_pinctrl_request(struct udevice * dev,int func,int flags)74 static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
75 {
76 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
77
78 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
79 switch (func) {
80 case PERIPH_ID_SPI0:
81 pinctrl_qca953x_spi_config(priv, flags);
82 break;
83 case PERIPH_ID_UART0:
84 pinctrl_qca953x_uart_config(priv, func);
85 break;
86 default:
87 return -EINVAL;
88 }
89
90 return 0;
91 }
92
qca953x_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)93 static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
94 struct udevice *periph)
95 {
96 u32 cell[2];
97 int ret;
98
99 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
100 "interrupts", cell, ARRAY_SIZE(cell));
101 if (ret < 0)
102 return -EINVAL;
103
104 switch (cell[0]) {
105 case 128:
106 return PERIPH_ID_UART0;
107 case 129:
108 return PERIPH_ID_SPI0;
109 }
110 return -ENOENT;
111 }
112
qca953x_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)113 static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
114 struct udevice *periph)
115 {
116 int func;
117
118 func = qca953x_pinctrl_get_periph_id(dev, periph);
119 if (func < 0)
120 return func;
121 return qca953x_pinctrl_request(dev, func, 0);
122 }
123
124 static struct pinctrl_ops qca953x_pinctrl_ops = {
125 .set_state_simple = qca953x_pinctrl_set_state_simple,
126 .request = qca953x_pinctrl_request,
127 .get_periph_id = qca953x_pinctrl_get_periph_id,
128 };
129
qca953x_pinctrl_probe(struct udevice * dev)130 static int qca953x_pinctrl_probe(struct udevice *dev)
131 {
132 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
133 fdt_addr_t addr;
134
135 addr = dev_read_addr(dev);
136 if (addr == FDT_ADDR_T_NONE)
137 return -EINVAL;
138
139 priv->regs = map_physmem(addr,
140 AR71XX_GPIO_SIZE,
141 MAP_NOCACHE);
142 return 0;
143 }
144
145 static const struct udevice_id qca953x_pinctrl_ids[] = {
146 { .compatible = "qca,qca953x-pinctrl" },
147 { }
148 };
149
150 U_BOOT_DRIVER(pinctrl_qca953x) = {
151 .name = "pinctrl_qca953x",
152 .id = UCLASS_PINCTRL,
153 .of_match = qca953x_pinctrl_ids,
154 .priv_auto = sizeof(struct qca953x_pinctrl_priv),
155 .ops = &qca953x_pinctrl_ops,
156 .probe = qca953x_pinctrl_probe,
157 };
158