1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ 10 #define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ 11 12 #define LPDDR4__DENALI_PHY_512_READ_MASK 0x000107FFU 13 #define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000107FFU 14 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU 15 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U 16 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U 17 #define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512 18 #define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 19 20 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U 21 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U 22 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U 23 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U 24 #define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U 25 #define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512 26 #define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0 27 28 #define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U 29 #define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U 30 #define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U 31 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512 32 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0 33 34 #define LPDDR4__DENALI_PHY_513_READ_MASK 0xFFFFFFFFU 35 #define LPDDR4__DENALI_PHY_513_WRITE_MASK 0xFFFFFFFFU 36 #define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU 37 #define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U 38 #define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U 39 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513 40 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0 41 42 #define LPDDR4__DENALI_PHY_514_READ_MASK 0x0FFFFFFFU 43 #define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x0FFFFFFFU 44 #define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU 45 #define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U 46 #define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U 47 #define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514 48 #define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0 49 50 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U 51 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U 52 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U 53 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514 54 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0 55 56 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U 57 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U 58 #define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U 59 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514 60 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 61 62 #define LPDDR4__DENALI_PHY_515_READ_MASK 0xFF7F07FFU 63 #define LPDDR4__DENALI_PHY_515_WRITE_MASK 0xFF7F07FFU 64 #define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU 65 #define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U 66 #define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U 67 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515 68 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0 69 70 #define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U 71 #define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U 72 #define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U 73 #define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515 74 #define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 75 76 #define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U 77 #define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U 78 #define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U 79 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515 80 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 81 82 #define LPDDR4__DENALI_PHY_516_READ_MASK 0x01000707U 83 #define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x01000707U 84 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U 85 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U 86 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U 87 #define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516 88 #define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 89 90 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U 91 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U 92 #define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U 93 #define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516 94 #define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 95 96 #define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U 97 #define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U 98 #define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U 99 #define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U 100 #define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U 101 #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516 102 #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0 103 104 #define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U 105 #define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U 106 #define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U 107 #define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U 108 #define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET 0U 109 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516 110 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0 111 112 #define LPDDR4__DENALI_PHY_517_READ_MASK 0x011F7F7FU 113 #define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x011F7F7FU 114 #define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU 115 #define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U 116 #define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U 117 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517 118 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0 119 120 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U 121 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U 122 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U 123 #define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517 124 #define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0 125 126 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U 127 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U 128 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U 129 #define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517 130 #define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0 131 132 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U 133 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U 134 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U 135 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U 136 #define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U 137 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517 138 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0 139 140 #define LPDDR4__DENALI_PHY_518_READ_MASK 0x01070301U 141 #define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x01070301U 142 #define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U 143 #define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U 144 #define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U 145 #define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U 146 #define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U 147 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518 148 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 149 150 #define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK 0x00000300U 151 #define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT 8U 152 #define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH 2U 153 #define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518 154 #define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0 155 156 #define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U 157 #define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U 158 #define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U 159 #define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518 160 #define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0 161 162 #define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK 0x01000000U 163 #define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT 24U 164 #define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH 1U 165 #define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR 0U 166 #define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET 0U 167 #define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518 168 #define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0 169 170 #define LPDDR4__DENALI_PHY_519_READ_MASK 0x07FFFFFFU 171 #define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x07FFFFFFU 172 #define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU 173 #define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT 0U 174 #define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH 27U 175 #define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519 176 #define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0 177 178 #define LPDDR4__DENALI_PHY_520_READ_MASK 0x0000003FU 179 #define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0000003FU 180 #define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU 181 #define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT 0U 182 #define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH 6U 183 #define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520 184 #define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0 185 186 #define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU 187 #define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU 188 #define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU 189 #define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U 190 #define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U 191 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521 192 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0 193 194 #define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU 195 #define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU 196 #define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU 197 #define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U 198 #define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U 199 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522 200 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 201 202 #define LPDDR4__DENALI_PHY_523_READ_MASK 0x07FF07FFU 203 #define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x07FF07FFU 204 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK 0x000007FFU 205 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT 0U 206 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH 11U 207 #define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523 208 #define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0 209 210 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U 211 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U 212 #define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U 213 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523 214 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0 215 216 #define LPDDR4__DENALI_PHY_524_READ_MASK 0x000007FFU 217 #define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x000007FFU 218 #define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU 219 #define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT 0U 220 #define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH 11U 221 #define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524 222 #define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0 223 224 #define LPDDR4__DENALI_PHY_525_READ_MASK 0x00FFFFFFU 225 #define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x00FFFFFFU 226 #define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU 227 #define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U 228 #define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U 229 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525 230 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0 231 232 #define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FFFFFFU 233 #define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FFFFFFU 234 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU 235 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U 236 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U 237 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526 238 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0 239 240 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U 241 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U 242 #define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U 243 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526 244 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0 245 246 #define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF0F03U 247 #define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF0F03U 248 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U 249 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U 250 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U 251 #define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527 252 #define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0 253 254 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U 255 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U 256 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U 257 #define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527 258 #define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0 259 260 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U 261 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U 262 #define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U 263 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527 264 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 265 266 #define LPDDR4__DENALI_PHY_528_READ_MASK 0x07000001U 267 #define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x07000001U 268 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U 269 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U 270 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U 271 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U 272 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U 273 #define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528 274 #define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0 275 276 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U 277 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U 278 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U 279 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U 280 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U 281 #define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528 282 #define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0 283 284 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U 285 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U 286 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U 287 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U 288 #define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U 289 #define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528 290 #define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0 291 292 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U 293 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U 294 #define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U 295 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528 296 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0 297 298 #define LPDDR4__DENALI_PHY_529_READ_MASK 0xFFFFFFFFU 299 #define LPDDR4__DENALI_PHY_529_WRITE_MASK 0xFFFFFFFFU 300 #define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK 0xFFFFFFFFU 301 #define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT 0U 302 #define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH 32U 303 #define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529 304 #define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0 305 306 #define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU 307 #define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU 308 #define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU 309 #define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT 0U 310 #define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH 32U 311 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530 312 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0 313 314 #define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU 315 #define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU 316 #define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU 317 #define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT 0U 318 #define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH 32U 319 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531 320 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0 321 322 #define LPDDR4__DENALI_PHY_532_READ_MASK 0x000FFFFFU 323 #define LPDDR4__DENALI_PHY_532_WRITE_MASK 0x000FFFFFU 324 #define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU 325 #define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT 0U 326 #define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH 20U 327 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532 328 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0 329 330 #define LPDDR4__DENALI_PHY_533_READ_MASK 0x000FFFFFU 331 #define LPDDR4__DENALI_PHY_533_WRITE_MASK 0x000FFFFFU 332 #define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU 333 #define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT 0U 334 #define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH 20U 335 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533 336 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0 337 338 #define LPDDR4__DENALI_PHY_534_READ_MASK 0x000FFFFFU 339 #define LPDDR4__DENALI_PHY_534_WRITE_MASK 0x000FFFFFU 340 #define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU 341 #define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT 0U 342 #define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH 20U 343 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534 344 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0 345 346 #define LPDDR4__DENALI_PHY_535_READ_MASK 0x000FFFFFU 347 #define LPDDR4__DENALI_PHY_535_WRITE_MASK 0x000FFFFFU 348 #define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU 349 #define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT 0U 350 #define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH 20U 351 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535 352 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0 353 354 #define LPDDR4__DENALI_PHY_536_READ_MASK 0x000FFFFFU 355 #define LPDDR4__DENALI_PHY_536_WRITE_MASK 0x000FFFFFU 356 #define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU 357 #define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT 0U 358 #define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH 20U 359 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536 360 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0 361 362 #define LPDDR4__DENALI_PHY_537_READ_MASK 0x000FFFFFU 363 #define LPDDR4__DENALI_PHY_537_WRITE_MASK 0x000FFFFFU 364 #define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU 365 #define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT 0U 366 #define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH 20U 367 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537 368 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0 369 370 #define LPDDR4__DENALI_PHY_538_READ_MASK 0x000FFFFFU 371 #define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x000FFFFFU 372 #define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU 373 #define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT 0U 374 #define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH 20U 375 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538 376 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0 377 378 #define LPDDR4__DENALI_PHY_539_READ_MASK 0x000FFFFFU 379 #define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x000FFFFFU 380 #define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU 381 #define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT 0U 382 #define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH 20U 383 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539 384 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0 385 386 #define LPDDR4__DENALI_PHY_540_READ_MASK 0x3FFFFFFFU 387 #define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x3FFFFFFFU 388 #define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU 389 #define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT 0U 390 #define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH 30U 391 #define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540 392 #define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0 393 394 #define LPDDR4__DENALI_PHY_541_READ_MASK 0x3F3F03FFU 395 #define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x3F3F03FFU 396 #define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU 397 #define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U 398 #define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U 399 #define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541 400 #define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0 401 402 #define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U 403 #define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT 16U 404 #define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH 6U 405 #define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541 406 #define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0 407 408 #define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U 409 #define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT 24U 410 #define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH 6U 411 #define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541 412 #define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0 413 414 #define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F0F3F3FU 415 #define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F0F3F3FU 416 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU 417 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U 418 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U 419 #define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542 420 #define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0 421 422 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U 423 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U 424 #define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U 425 #define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542 426 #define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0 427 428 #define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U 429 #define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U 430 #define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U 431 #define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542 432 #define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0 433 434 #define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U 435 #define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U 436 #define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U 437 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542 438 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0 439 440 #define LPDDR4__DENALI_PHY_543_READ_MASK 0x0000003FU 441 #define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0000003FU 442 #define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x0000003FU 443 #define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 0U 444 #define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U 445 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543 446 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0 447 448 #define LPDDR4__DENALI_PHY_544_READ_MASK 0x0707FFFFU 449 #define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x0707FFFFU 450 #define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU 451 #define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT 0U 452 #define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH 8U 453 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544 454 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0 455 456 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK 0x0007FF00U 457 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT 8U 458 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U 459 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544 460 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0 461 462 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x07000000U 463 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 24U 464 #define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U 465 #define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544 466 #define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0 467 468 #define LPDDR4__DENALI_PHY_545_READ_MASK 0x1F07FF1FU 469 #define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x1F07FF1FU 470 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU 471 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U 472 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U 473 #define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545 474 #define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0 475 476 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U 477 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U 478 #define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 479 #define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545 480 #define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0 481 482 #define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U 483 #define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U 484 #define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U 485 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545 486 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0 487 488 #define LPDDR4__DENALI_PHY_546_READ_MASK 0x001F07FFU 489 #define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x001F07FFU 490 #define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU 491 #define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U 492 #define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 493 #define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546 494 #define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0 495 496 #define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U 497 #define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U 498 #define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U 499 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546 500 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0 501 502 #define LPDDR4__DENALI_PHY_547_READ_MASK 0x001F07FFU 503 #define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x001F07FFU 504 #define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU 505 #define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U 506 #define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 507 #define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547 508 #define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0 509 510 #define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U 511 #define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U 512 #define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U 513 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547 514 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0 515 516 #define LPDDR4__DENALI_PHY_548_READ_MASK 0x001F07FFU 517 #define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x001F07FFU 518 #define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU 519 #define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U 520 #define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 521 #define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548 522 #define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0 523 524 #define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U 525 #define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U 526 #define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U 527 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548 528 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0 529 530 #define LPDDR4__DENALI_PHY_549_READ_MASK 0x001F07FFU 531 #define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x001F07FFU 532 #define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU 533 #define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U 534 #define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 535 #define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549 536 #define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0 537 538 #define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U 539 #define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U 540 #define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U 541 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549 542 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0 543 544 #define LPDDR4__DENALI_PHY_550_READ_MASK 0x000F07FFU 545 #define LPDDR4__DENALI_PHY_550_WRITE_MASK 0x000F07FFU 546 #define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU 547 #define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U 548 #define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U 549 #define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550 550 #define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0 551 552 #define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U 553 #define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U 554 #define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U 555 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550 556 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0 557 558 #define LPDDR4__DENALI_PHY_551_READ_MASK 0xFF3F07FFU 559 #define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFF3F07FFU 560 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU 561 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U 562 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U 563 #define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551 564 #define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0 565 566 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U 567 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U 568 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U 569 #define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551 570 #define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0 571 572 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U 573 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U 574 #define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U 575 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551 576 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0 577 578 #define LPDDR4__DENALI_PHY_552_READ_MASK 0x0103FFFFU 579 #define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0103FFFFU 580 #define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU 581 #define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U 582 #define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U 583 #define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552 584 #define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 585 586 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U 587 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U 588 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U 589 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552 590 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0 591 592 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U 593 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U 594 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U 595 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U 596 #define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U 597 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552 598 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0 599 600 #define LPDDR4__DENALI_PHY_553_READ_MASK 0x0000000FU 601 #define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x0000000FU 602 #define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU 603 #define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U 604 #define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U 605 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553 606 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0 607 608 #define LPDDR4__DENALI_PHY_554_READ_MASK 0x0000010FU 609 #define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0000010FU 610 #define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU 611 #define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U 612 #define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U 613 #define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554 614 #define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0 615 616 #define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U 617 #define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U 618 #define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U 619 #define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U 620 #define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U 621 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554 622 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0 623 624 #endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */ 625