1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #ifndef CPS_DRV_H_
10 #define CPS_DRV_H_
11
12 #ifdef DEMO_TB
13 #include <cdn_demo.h>
14 #else
15 #include <asm/io.h>
16 #endif
17
18 #define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
19
20 #define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
21
22 #define CPS_FLD_MASK(fld) (fld ## _MASK)
23 #define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
24 #define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
25 #define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
26 #define CPS_FLD_WOSET(fld) (fld ## _WOSET)
27
28 #define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
29 (u32)(CPS_FLD_SHIFT(fld)), \
30 (u32)(reg_value)))
31
32 #define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
33 (u32)(CPS_FLD_SHIFT(fld)), \
34 (u32)(reg_value), (u32)(value)))
35
36 #define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
37 (u32)(CPS_FLD_MASK(fld)), \
38 (u32)(CPS_FLD_WOCLR(fld)), \
39 (u32)(reg_value)))
40
41 #ifdef CLR_USED
42 #define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
43 (u32)(CPS_FLD_MASK(fld)), \
44 (u32)(CPS_FLD_WOSET(fld)), \
45 (u32)(CPS_FLD_WOCLR(fld)), \
46 (u32)(reg_value)))
47
48 #endif
49 static inline u32 cps_regread(volatile u32 *reg);
cps_regread(volatile u32 * reg)50 static inline u32 cps_regread(volatile u32 *reg)
51 {
52 return readl(reg);
53 }
54
55 static inline void cps_regwrite(volatile u32 *reg, u32 value);
cps_regwrite(volatile u32 * reg,u32 value)56 static inline void cps_regwrite(volatile u32 *reg, u32 value)
57 {
58 writel(value, reg);
59 }
60
61 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
cps_fldread(u32 mask,u32 shift,u32 reg_value)62 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
63 {
64 u32 result = (reg_value & mask) >> shift;
65
66 return result;
67 }
68
69 static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
cps_fldwrite(u32 mask,u32 shift,u32 reg_value,u32 value)70 static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
71 {
72 u32 new_value = (value << shift) & mask;
73
74 new_value = (reg_value & ~mask) | new_value;
75 return new_value;
76 }
77
78 static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
cps_fldset(u32 width,u32 mask,u32 is_woclr,u32 reg_value)79 static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
80 {
81 u32 new_value = reg_value;
82
83 if ((width == 1U) && (is_woclr == 0U))
84 new_value |= mask;
85
86 return new_value;
87 }
88
89 #ifdef CLR_USED
90 static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
cps_fldclear(u32 width,u32 mask,u32 is_woset,u32 is_woclr,u32 reg_value)91 static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
92 {
93 u32 new_value = reg_value;
94
95 if ((width == 1U) && (is_woset == 0U))
96 new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
97
98 return new_value;
99 }
100 #endif /* CLR_USED */
101
102 #endif /* CPS_DRV_H_ */
103