1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <log.h>
10 #include <asm-generic/io.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <malloc.h>
14 #include <reset.h>
15 #include <spi.h>
16 #include <spi-mem.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/sizes.h>
21 #include "cadence_qspi.h"
22
23 #define NSEC_PER_SEC 1000000000L
24
25 #define CQSPI_STIG_READ 0
26 #define CQSPI_STIG_WRITE 1
27 #define CQSPI_READ 2
28 #define CQSPI_WRITE 3
29
cadence_spi_write_speed(struct udevice * bus,uint hz)30 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
31 {
32 struct cadence_spi_plat *plat = dev_get_plat(bus);
33 struct cadence_spi_priv *priv = dev_get_priv(bus);
34
35 cadence_qspi_apb_config_baudrate_div(priv->regbase,
36 plat->ref_clk_hz, hz);
37
38 /* Reconfigure delay timing if speed is changed. */
39 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
40 plat->tshsl_ns, plat->tsd2d_ns,
41 plat->tchsh_ns, plat->tslch_ns);
42
43 return 0;
44 }
45
cadence_spi_read_id(struct cadence_spi_plat * plat,u8 len,u8 * idcode)46 static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len,
47 u8 *idcode)
48 {
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
50 SPI_MEM_OP_NO_ADDR,
51 SPI_MEM_OP_NO_DUMMY,
52 SPI_MEM_OP_DATA_IN(len, idcode, 1));
53
54 return cadence_qspi_apb_command_read(plat, &op);
55 }
56
57 /* Calibration sequence to determine the read data capture delay register */
spi_calibration(struct udevice * bus,uint hz)58 static int spi_calibration(struct udevice *bus, uint hz)
59 {
60 struct cadence_spi_priv *priv = dev_get_priv(bus);
61 struct cadence_spi_plat *plat = dev_get_plat(bus);
62 void *base = priv->regbase;
63 unsigned int idcode = 0, temp = 0;
64 int err = 0, i, range_lo = -1, range_hi = -1;
65
66 /* start with slowest clock (1 MHz) */
67 cadence_spi_write_speed(bus, 1000000);
68
69 /* configure the read data capture delay register to 0 */
70 cadence_qspi_apb_readdata_capture(base, 1, 0);
71
72 /* Enable QSPI */
73 cadence_qspi_apb_controller_enable(base);
74
75 /* read the ID which will be our golden value */
76 err = cadence_spi_read_id(plat, 3, (u8 *)&idcode);
77 if (err) {
78 puts("SF: Calibration failed (read)\n");
79 return err;
80 }
81
82 /* use back the intended clock and find low range */
83 cadence_spi_write_speed(bus, hz);
84 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
85 /* Disable QSPI */
86 cadence_qspi_apb_controller_disable(base);
87
88 /* reconfigure the read data capture delay register */
89 cadence_qspi_apb_readdata_capture(base, 1, i);
90
91 /* Enable back QSPI */
92 cadence_qspi_apb_controller_enable(base);
93
94 /* issue a RDID to get the ID value */
95 err = cadence_spi_read_id(plat, 3, (u8 *)&temp);
96 if (err) {
97 puts("SF: Calibration failed (read)\n");
98 return err;
99 }
100
101 /* search for range lo */
102 if (range_lo == -1 && temp == idcode) {
103 range_lo = i;
104 continue;
105 }
106
107 /* search for range hi */
108 if (range_lo != -1 && temp != idcode) {
109 range_hi = i - 1;
110 break;
111 }
112 range_hi = i;
113 }
114
115 if (range_lo == -1) {
116 puts("SF: Calibration failed (low range)\n");
117 return err;
118 }
119
120 /* Disable QSPI for subsequent initialization */
121 cadence_qspi_apb_controller_disable(base);
122
123 /* configure the final value for read data capture delay register */
124 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
125 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
126 (range_hi + range_lo) / 2, range_lo, range_hi);
127
128 /* just to ensure we do once only when speed or chip select change */
129 priv->qspi_calibrated_hz = hz;
130 priv->qspi_calibrated_cs = spi_chip_select(bus);
131
132 return 0;
133 }
134
cadence_spi_set_speed(struct udevice * bus,uint hz)135 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
136 {
137 struct cadence_spi_plat *plat = dev_get_plat(bus);
138 struct cadence_spi_priv *priv = dev_get_priv(bus);
139 int err;
140
141 if (hz > plat->max_hz)
142 hz = plat->max_hz;
143
144 /* Disable QSPI */
145 cadence_qspi_apb_controller_disable(priv->regbase);
146
147 /*
148 * If the device tree already provides a read delay value, use that
149 * instead of calibrating.
150 */
151 if (plat->read_delay >= 0) {
152 cadence_spi_write_speed(bus, hz);
153 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
154 plat->read_delay);
155 } else if (priv->previous_hz != hz ||
156 priv->qspi_calibrated_hz != hz ||
157 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
158 /*
159 * Calibration required for different current SCLK speed,
160 * requested SCLK speed or chip select
161 */
162 err = spi_calibration(bus, hz);
163 if (err)
164 return err;
165
166 /* prevent calibration run when same as previous request */
167 priv->previous_hz = hz;
168 }
169
170 /* Enable QSPI */
171 cadence_qspi_apb_controller_enable(priv->regbase);
172
173 debug("%s: speed=%d\n", __func__, hz);
174
175 return 0;
176 }
177
cadence_spi_probe(struct udevice * bus)178 static int cadence_spi_probe(struct udevice *bus)
179 {
180 struct cadence_spi_plat *plat = dev_get_plat(bus);
181 struct cadence_spi_priv *priv = dev_get_priv(bus);
182 struct clk clk;
183 int ret;
184
185 priv->regbase = plat->regbase;
186 priv->ahbbase = plat->ahbbase;
187
188 if (plat->ref_clk_hz == 0) {
189 ret = clk_get_by_index(bus, 0, &clk);
190 if (ret) {
191 #ifdef CONFIG_CQSPI_REF_CLK
192 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
193 #else
194 return ret;
195 #endif
196 } else {
197 plat->ref_clk_hz = clk_get_rate(&clk);
198 clk_free(&clk);
199 if (IS_ERR_VALUE(plat->ref_clk_hz))
200 return plat->ref_clk_hz;
201 }
202 }
203
204 ret = reset_get_bulk(bus, &priv->resets);
205 if (ret)
206 dev_warn(bus, "Can't get reset: %d\n", ret);
207 else
208 reset_deassert_bulk(&priv->resets);
209
210 if (!priv->qspi_is_init) {
211 cadence_qspi_apb_controller_init(plat);
212 priv->qspi_is_init = 1;
213 }
214
215 plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz);
216
217 return 0;
218 }
219
cadence_spi_remove(struct udevice * dev)220 static int cadence_spi_remove(struct udevice *dev)
221 {
222 struct cadence_spi_priv *priv = dev_get_priv(dev);
223
224 return reset_release_bulk(&priv->resets);
225 }
226
cadence_spi_set_mode(struct udevice * bus,uint mode)227 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
228 {
229 struct cadence_spi_plat *plat = dev_get_plat(bus);
230 struct cadence_spi_priv *priv = dev_get_priv(bus);
231
232 /* Disable QSPI */
233 cadence_qspi_apb_controller_disable(priv->regbase);
234
235 /* Set SPI mode */
236 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
237
238 /* Enable Direct Access Controller */
239 if (plat->use_dac_mode)
240 cadence_qspi_apb_dac_mode_enable(priv->regbase);
241
242 /* Enable QSPI */
243 cadence_qspi_apb_controller_enable(priv->regbase);
244
245 return 0;
246 }
247
cadence_spi_mem_exec_op(struct spi_slave * spi,const struct spi_mem_op * op)248 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
249 const struct spi_mem_op *op)
250 {
251 struct udevice *bus = spi->dev->parent;
252 struct cadence_spi_plat *plat = dev_get_plat(bus);
253 struct cadence_spi_priv *priv = dev_get_priv(bus);
254 void *base = priv->regbase;
255 int err = 0;
256 u32 mode;
257
258 /* Set Chip select */
259 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
260 plat->is_decoded_cs);
261
262 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
263 if (!op->addr.nbytes)
264 mode = CQSPI_STIG_READ;
265 else
266 mode = CQSPI_READ;
267 } else {
268 if (!op->addr.nbytes || !op->data.buf.out)
269 mode = CQSPI_STIG_WRITE;
270 else
271 mode = CQSPI_WRITE;
272 }
273
274 switch (mode) {
275 case CQSPI_STIG_READ:
276 err = cadence_qspi_apb_command_read_setup(plat, op);
277 if (!err)
278 err = cadence_qspi_apb_command_read(plat, op);
279 break;
280 case CQSPI_STIG_WRITE:
281 err = cadence_qspi_apb_command_write_setup(plat, op);
282 if (!err)
283 err = cadence_qspi_apb_command_write(plat, op);
284 break;
285 case CQSPI_READ:
286 err = cadence_qspi_apb_read_setup(plat, op);
287 if (!err)
288 err = cadence_qspi_apb_read_execute(plat, op);
289 break;
290 case CQSPI_WRITE:
291 err = cadence_qspi_apb_write_setup(plat, op);
292 if (!err)
293 err = cadence_qspi_apb_write_execute(plat, op);
294 break;
295 default:
296 err = -1;
297 break;
298 }
299
300 return err;
301 }
302
cadence_spi_mem_supports_op(struct spi_slave * slave,const struct spi_mem_op * op)303 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
304 const struct spi_mem_op *op)
305 {
306 bool all_true, all_false;
307
308 all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
309 op->data.dtr;
310 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
311 !op->data.dtr;
312
313 /* Mixed DTR modes not supported. */
314 if (!(all_true || all_false))
315 return false;
316
317 if (all_true)
318 return spi_mem_dtr_supports_op(slave, op);
319 else
320 return spi_mem_default_supports_op(slave, op);
321 }
322
cadence_spi_of_to_plat(struct udevice * bus)323 static int cadence_spi_of_to_plat(struct udevice *bus)
324 {
325 struct cadence_spi_plat *plat = dev_get_plat(bus);
326 ofnode subnode;
327
328 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
329 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
330 &plat->ahbsize);
331 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
332 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
333 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
334 plat->trigger_address = dev_read_u32_default(bus,
335 "cdns,trigger-address",
336 0);
337 /* Use DAC mode only when MMIO window is at least 8M wide */
338 if (plat->ahbsize >= SZ_8M)
339 plat->use_dac_mode = true;
340
341 /* All other paramters are embedded in the child node */
342 subnode = dev_read_first_subnode(bus);
343 if (!ofnode_valid(subnode)) {
344 printf("Error: subnode with SPI flash config missing!\n");
345 return -ENODEV;
346 }
347
348 /* Use 500 KHz as a suitable default */
349 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
350 500000);
351
352 /* Read other parameters from DT */
353 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
354 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
355 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
356 200);
357 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
358 255);
359 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
360 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
361 /*
362 * Read delay should be an unsigned value but we use a signed integer
363 * so that negative values can indicate that the device tree did not
364 * specify any signed values and we need to perform the calibration
365 * sequence to find it out.
366 */
367 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
368 -1);
369
370 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
371 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
372 plat->page_size);
373
374 return 0;
375 }
376
377 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
378 .exec_op = cadence_spi_mem_exec_op,
379 .supports_op = cadence_spi_mem_supports_op,
380 };
381
382 static const struct dm_spi_ops cadence_spi_ops = {
383 .set_speed = cadence_spi_set_speed,
384 .set_mode = cadence_spi_set_mode,
385 .mem_ops = &cadence_spi_mem_ops,
386 /*
387 * cs_info is not needed, since we require all chip selects to be
388 * in the device tree explicitly
389 */
390 };
391
392 static const struct udevice_id cadence_spi_ids[] = {
393 { .compatible = "cdns,qspi-nor" },
394 { .compatible = "ti,am654-ospi" },
395 { }
396 };
397
398 U_BOOT_DRIVER(cadence_spi) = {
399 .name = "cadence_spi",
400 .id = UCLASS_SPI,
401 .of_match = cadence_spi_ids,
402 .ops = &cadence_spi_ops,
403 .of_to_plat = cadence_spi_of_to_plat,
404 .plat_auto = sizeof(struct cadence_spi_plat),
405 .priv_auto = sizeof(struct cadence_spi_priv),
406 .probe = cadence_spi_probe,
407 .remove = cadence_spi_remove,
408 .flags = DM_FLAG_OS_PREPARE,
409 };
410