1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <asm/mpc8xxx_spi.h>
15 #include <asm-generic/gpio.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19
20 enum {
21 SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
22 SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
23 };
24
25 enum {
26 SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
27 SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
28 SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
29 SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
30 SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
31 SPI_MODE_MS = BIT(31 - 6), /* Always master */
32 SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
33
34 SPI_MODE_LEN_MASK = 0xf00000,
35 SPI_MODE_LEN_SHIFT = 20,
36 SPI_MODE_PM_SHIFT = 16,
37 SPI_MODE_PM_MASK = 0xf0000,
38
39 SPI_COM_LST = BIT(31 - 9),
40 };
41
42 struct mpc8xxx_priv {
43 spi8xxx_t *spi;
44 struct gpio_desc gpios[16];
45 int cs_count;
46 ulong clk_rate;
47 };
48
49 #define SPI_TIMEOUT 1000
50
mpc8xxx_spi_of_to_plat(struct udevice * dev)51 static int mpc8xxx_spi_of_to_plat(struct udevice *dev)
52 {
53 struct mpc8xxx_priv *priv = dev_get_priv(dev);
54 struct clk clk;
55 int ret;
56
57 priv->spi = (spi8xxx_t *)dev_read_addr(dev);
58
59 ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
60 ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
61 if (ret < 0)
62 return -EINVAL;
63
64 priv->cs_count = ret;
65
66 ret = clk_get_by_index(dev, 0, &clk);
67 if (ret) {
68 dev_err(dev, "%s: clock not defined\n", __func__);
69 return ret;
70 }
71
72 priv->clk_rate = clk_get_rate(&clk);
73 if (!priv->clk_rate) {
74 dev_err(dev, "%s: failed to get clock rate\n", __func__);
75 return -EINVAL;
76 }
77
78 return 0;
79 }
80
mpc8xxx_spi_probe(struct udevice * dev)81 static int mpc8xxx_spi_probe(struct udevice *dev)
82 {
83 struct mpc8xxx_priv *priv = dev_get_priv(dev);
84 spi8xxx_t *spi = priv->spi;
85
86 /*
87 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
88 * some registers
89 */
90 out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
91
92 /* set len to 8 bits */
93 setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
94
95 setbits_be32(&spi->mode, SPI_MODE_EN);
96
97 /* Clear all SPI events */
98 setbits_be32(&priv->spi->event, 0xffffffff);
99 /* Mask all SPI interrupts */
100 clrbits_be32(&priv->spi->mask, 0xffffffff);
101 /* LST bit doesn't do anything, so disregard */
102 out_be32(&priv->spi->com, 0);
103
104 return 0;
105 }
106
mpc8xxx_spi_cs_activate(struct udevice * dev)107 static void mpc8xxx_spi_cs_activate(struct udevice *dev)
108 {
109 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
110 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
111
112 dm_gpio_set_value(&priv->gpios[plat->cs], 1);
113 }
114
mpc8xxx_spi_cs_deactivate(struct udevice * dev)115 static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
116 {
117 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
118 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
119
120 dm_gpio_set_value(&priv->gpios[plat->cs], 0);
121 }
122
mpc8xxx_spi_xfer(struct udevice * dev,uint bitlen,const void * dout,void * din,ulong flags)123 static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
124 const void *dout, void *din, ulong flags)
125 {
126 struct udevice *bus = dev->parent;
127 struct mpc8xxx_priv *priv = dev_get_priv(bus);
128 spi8xxx_t *spi = priv->spi;
129 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
130 u32 tmpdin = 0, tmpdout = 0, n;
131 const u8 *cout = dout;
132 u8 *cin = din;
133
134 debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
135 bus->name, plat->cs, (uint)dout, (uint)din, bitlen);
136 if (plat->cs >= priv->cs_count) {
137 dev_err(dev, "chip select index %d too large (cs_count=%d)\n",
138 plat->cs, priv->cs_count);
139 return -EINVAL;
140 }
141 if (bitlen % 8) {
142 printf("*** spi_xfer: bitlen must be multiple of 8\n");
143 return -ENOTSUPP;
144 }
145
146 if (flags & SPI_XFER_BEGIN)
147 mpc8xxx_spi_cs_activate(dev);
148
149 /* Clear all SPI events */
150 setbits_be32(&spi->event, 0xffffffff);
151 n = bitlen / 8;
152
153 /* Handle data in 8-bit chunks */
154 while (n--) {
155 ulong start;
156
157 if (cout)
158 tmpdout = *cout++;
159
160 /* Write the data out */
161 out_be32(&spi->tx, tmpdout);
162
163 debug("*** %s: ... %08x written\n", __func__, tmpdout);
164
165 /*
166 * Wait for SPI transmit to get out
167 * or time out (1 second = 1000 ms)
168 * The NE event must be read and cleared first
169 */
170 start = get_timer(0);
171 do {
172 u32 event = in_be32(&spi->event);
173 bool have_ne = event & SPI_EV_NE;
174 bool have_nf = event & SPI_EV_NF;
175
176 if (!have_ne)
177 continue;
178
179 tmpdin = in_be32(&spi->rx);
180 setbits_be32(&spi->event, SPI_EV_NE);
181
182 if (cin)
183 *cin++ = tmpdin;
184
185 /*
186 * Only bail when we've had both NE and NF events.
187 * This will cause timeouts on RO devices, so maybe
188 * in the future put an arbitrary delay after writing
189 * the device. Arbitrary delays suck, though...
190 */
191 if (have_nf)
192 break;
193
194 mdelay(1);
195 } while (get_timer(start) < SPI_TIMEOUT);
196
197 if (get_timer(start) >= SPI_TIMEOUT) {
198 debug("*** %s: Time out during SPI transfer\n",
199 __func__);
200 return -ETIMEDOUT;
201 }
202
203 debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
204 }
205
206 if (flags & SPI_XFER_END)
207 mpc8xxx_spi_cs_deactivate(dev);
208
209 return 0;
210 }
211
mpc8xxx_spi_set_speed(struct udevice * dev,uint speed)212 static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
213 {
214 struct mpc8xxx_priv *priv = dev_get_priv(dev);
215 spi8xxx_t *spi = priv->spi;
216 u32 bits, mask, div16, pm;
217 u32 mode;
218 ulong clk;
219
220 clk = priv->clk_rate;
221 if (clk / 64 > speed) {
222 div16 = SPI_MODE_DIV16;
223 clk /= 16;
224 } else {
225 div16 = 0;
226 }
227 pm = (clk - 1)/(4*speed) + 1;
228 if (pm > 16) {
229 dev_err(dev, "requested speed %u too small\n", speed);
230 return -EINVAL;
231 }
232 pm--;
233
234 bits = div16 | (pm << SPI_MODE_PM_SHIFT);
235 mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK;
236 mode = in_be32(&spi->mode);
237 if ((mode & mask) != bits) {
238 /* Must clear mode[EN] while changing speed. */
239 mode &= ~(mask | SPI_MODE_EN);
240 out_be32(&spi->mode, mode);
241 mode |= bits;
242 out_be32(&spi->mode, mode);
243 mode |= SPI_MODE_EN;
244 out_be32(&spi->mode, mode);
245 }
246
247 debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n",
248 speed, priv->clk_rate, div16 ? "16*" : "", pm + 1,
249 clk/(4*(pm + 1)));
250
251 return 0;
252 }
253
mpc8xxx_spi_set_mode(struct udevice * dev,uint mode)254 static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
255 {
256 /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
257 * SPI_CPOL (for clock polarity) should work
258 */
259 return 0;
260 }
261
262 static const struct dm_spi_ops mpc8xxx_spi_ops = {
263 .xfer = mpc8xxx_spi_xfer,
264 .set_speed = mpc8xxx_spi_set_speed,
265 .set_mode = mpc8xxx_spi_set_mode,
266 /*
267 * cs_info is not needed, since we require all chip selects to be
268 * in the device tree explicitly
269 */
270 };
271
272 static const struct udevice_id mpc8xxx_spi_ids[] = {
273 { .compatible = "fsl,spi" },
274 { }
275 };
276
277 U_BOOT_DRIVER(mpc8xxx_spi) = {
278 .name = "mpc8xxx_spi",
279 .id = UCLASS_SPI,
280 .of_match = mpc8xxx_spi_ids,
281 .ops = &mpc8xxx_spi_ops,
282 .of_to_plat = mpc8xxx_spi_of_to_plat,
283 .probe = mpc8xxx_spi_probe,
284 .priv_auto = sizeof(struct mpc8xxx_priv),
285 };
286