1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 *
5 * Michael Kurz, <michi.kurz@gmail.com>
6 *
7 * STM32 QSPI driver
8 */
9
10 #define LOG_CATEGORY UCLASS_SPI
11
12 #include <common.h>
13 #include <clk.h>
14 #include <dm.h>
15 #include <log.h>
16 #include <reset.h>
17 #include <spi.h>
18 #include <spi-mem.h>
19 #include <watchdog.h>
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/ioport.h>
25 #include <linux/sizes.h>
26
27 struct stm32_qspi_regs {
28 u32 cr; /* 0x00 */
29 u32 dcr; /* 0x04 */
30 u32 sr; /* 0x08 */
31 u32 fcr; /* 0x0C */
32 u32 dlr; /* 0x10 */
33 u32 ccr; /* 0x14 */
34 u32 ar; /* 0x18 */
35 u32 abr; /* 0x1C */
36 u32 dr; /* 0x20 */
37 u32 psmkr; /* 0x24 */
38 u32 psmar; /* 0x28 */
39 u32 pir; /* 0x2C */
40 u32 lptr; /* 0x30 */
41 };
42
43 /*
44 * QUADSPI control register
45 */
46 #define STM32_QSPI_CR_EN BIT(0)
47 #define STM32_QSPI_CR_ABORT BIT(1)
48 #define STM32_QSPI_CR_DMAEN BIT(2)
49 #define STM32_QSPI_CR_TCEN BIT(3)
50 #define STM32_QSPI_CR_SSHIFT BIT(4)
51 #define STM32_QSPI_CR_DFM BIT(6)
52 #define STM32_QSPI_CR_FSEL BIT(7)
53 #define STM32_QSPI_CR_FTHRES_SHIFT 8
54 #define STM32_QSPI_CR_TEIE BIT(16)
55 #define STM32_QSPI_CR_TCIE BIT(17)
56 #define STM32_QSPI_CR_FTIE BIT(18)
57 #define STM32_QSPI_CR_SMIE BIT(19)
58 #define STM32_QSPI_CR_TOIE BIT(20)
59 #define STM32_QSPI_CR_APMS BIT(22)
60 #define STM32_QSPI_CR_PMM BIT(23)
61 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
62 #define STM32_QSPI_CR_PRESCALER_SHIFT 24
63
64 /*
65 * QUADSPI device configuration register
66 */
67 #define STM32_QSPI_DCR_CKMODE BIT(0)
68 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
69 #define STM32_QSPI_DCR_CSHT_SHIFT 8
70 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
71 #define STM32_QSPI_DCR_FSIZE_SHIFT 16
72
73 /*
74 * QUADSPI status register
75 */
76 #define STM32_QSPI_SR_TEF BIT(0)
77 #define STM32_QSPI_SR_TCF BIT(1)
78 #define STM32_QSPI_SR_FTF BIT(2)
79 #define STM32_QSPI_SR_SMF BIT(3)
80 #define STM32_QSPI_SR_TOF BIT(4)
81 #define STM32_QSPI_SR_BUSY BIT(5)
82
83 /*
84 * QUADSPI flag clear register
85 */
86 #define STM32_QSPI_FCR_CTEF BIT(0)
87 #define STM32_QSPI_FCR_CTCF BIT(1)
88 #define STM32_QSPI_FCR_CSMF BIT(3)
89 #define STM32_QSPI_FCR_CTOF BIT(4)
90
91 /*
92 * QUADSPI communication configuration register
93 */
94 #define STM32_QSPI_CCR_DDRM BIT(31)
95 #define STM32_QSPI_CCR_DHHC BIT(30)
96 #define STM32_QSPI_CCR_SIOO BIT(28)
97 #define STM32_QSPI_CCR_FMODE_SHIFT 26
98 #define STM32_QSPI_CCR_DMODE_SHIFT 24
99 #define STM32_QSPI_CCR_DCYC_SHIFT 18
100 #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
101 #define STM32_QSPI_CCR_ABMODE_SHIFT 14
102 #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
103 #define STM32_QSPI_CCR_ADMODE_SHIFT 10
104 #define STM32_QSPI_CCR_IMODE_SHIFT 8
105
106 #define STM32_QSPI_CCR_IND_WRITE 0
107 #define STM32_QSPI_CCR_IND_READ 1
108 #define STM32_QSPI_CCR_MEM_MAP 3
109
110 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
111 #define STM32_QSPI_MAX_CHIP 2
112
113 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
114 #define STM32_QSPI_CMD_TIMEOUT_US 1000000
115 #define STM32_BUSY_TIMEOUT_US 100000
116 #define STM32_ABT_TIMEOUT_US 100000
117
118 struct stm32_qspi_flash {
119 u32 cr;
120 u32 dcr;
121 bool initialized;
122 };
123
124 struct stm32_qspi_priv {
125 struct stm32_qspi_regs *regs;
126 struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
127 void __iomem *mm_base;
128 resource_size_t mm_size;
129 ulong clock_rate;
130 int cs_used;
131 };
132
_stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv * priv)133 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
134 {
135 u32 sr;
136 int ret;
137
138 ret = readl_poll_timeout(&priv->regs->sr, sr,
139 !(sr & STM32_QSPI_SR_BUSY),
140 STM32_BUSY_TIMEOUT_US);
141 if (ret)
142 log_err("busy timeout (stat:%#x)\n", sr);
143
144 return ret;
145 }
146
_stm32_qspi_wait_cmd(struct stm32_qspi_priv * priv,const struct spi_mem_op * op)147 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
148 const struct spi_mem_op *op)
149 {
150 u32 sr;
151 int ret = 0;
152
153 if (op->data.nbytes) {
154 ret = readl_poll_timeout(&priv->regs->sr, sr,
155 sr & STM32_QSPI_SR_TCF,
156 STM32_QSPI_CMD_TIMEOUT_US);
157 if (ret) {
158 log_err("cmd timeout (stat:%#x)\n", sr);
159 } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
160 log_err("transfer error (stat:%#x)\n", sr);
161 ret = -EIO;
162 }
163 /* clear flags */
164 writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
165 }
166
167 if (!ret)
168 ret = _stm32_qspi_wait_for_not_busy(priv);
169
170 return ret;
171 }
172
_stm32_qspi_read_fifo(u8 * val,void __iomem * addr)173 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
174 {
175 *val = readb(addr);
176 WATCHDOG_RESET();
177 }
178
_stm32_qspi_write_fifo(u8 * val,void __iomem * addr)179 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
180 {
181 writeb(*val, addr);
182 }
183
_stm32_qspi_poll(struct stm32_qspi_priv * priv,const struct spi_mem_op * op)184 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
185 const struct spi_mem_op *op)
186 {
187 void (*fifo)(u8 *val, void __iomem *addr);
188 u32 len = op->data.nbytes, sr;
189 u8 *buf;
190 int ret;
191
192 if (op->data.dir == SPI_MEM_DATA_IN) {
193 fifo = _stm32_qspi_read_fifo;
194 buf = op->data.buf.in;
195
196 } else {
197 fifo = _stm32_qspi_write_fifo;
198 buf = (u8 *)op->data.buf.out;
199 }
200
201 while (len--) {
202 ret = readl_poll_timeout(&priv->regs->sr, sr,
203 sr & STM32_QSPI_SR_FTF,
204 STM32_QSPI_FIFO_TIMEOUT_US);
205 if (ret) {
206 log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
207 return ret;
208 }
209
210 fifo(buf++, &priv->regs->dr);
211 }
212
213 return 0;
214 }
215
stm32_qspi_mm(struct stm32_qspi_priv * priv,const struct spi_mem_op * op)216 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
217 const struct spi_mem_op *op)
218 {
219 memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
220 op->data.nbytes);
221
222 return 0;
223 }
224
_stm32_qspi_tx(struct stm32_qspi_priv * priv,const struct spi_mem_op * op,u8 mode)225 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
226 const struct spi_mem_op *op,
227 u8 mode)
228 {
229 if (!op->data.nbytes)
230 return 0;
231
232 if (mode == STM32_QSPI_CCR_MEM_MAP)
233 return stm32_qspi_mm(priv, op);
234
235 return _stm32_qspi_poll(priv, op);
236 }
237
_stm32_qspi_get_mode(u8 buswidth)238 static int _stm32_qspi_get_mode(u8 buswidth)
239 {
240 if (buswidth == 4)
241 return 3;
242
243 return buswidth;
244 }
245
stm32_qspi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)246 static int stm32_qspi_exec_op(struct spi_slave *slave,
247 const struct spi_mem_op *op)
248 {
249 struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
250 u32 cr, ccr, addr_max;
251 u8 mode = STM32_QSPI_CCR_IND_WRITE;
252 int timeout, ret;
253
254 dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
255 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
256 op->dummy.buswidth, op->data.buswidth,
257 op->addr.val, op->data.nbytes);
258
259 ret = _stm32_qspi_wait_for_not_busy(priv);
260 if (ret)
261 return ret;
262
263 addr_max = op->addr.val + op->data.nbytes + 1;
264
265 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
266 if (addr_max < priv->mm_size && op->addr.buswidth)
267 mode = STM32_QSPI_CCR_MEM_MAP;
268 else
269 mode = STM32_QSPI_CCR_IND_READ;
270 }
271
272 if (op->data.nbytes)
273 writel(op->data.nbytes - 1, &priv->regs->dlr);
274
275 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
276 ccr |= op->cmd.opcode;
277 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
278 << STM32_QSPI_CCR_IMODE_SHIFT);
279
280 if (op->addr.nbytes) {
281 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
282 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
283 << STM32_QSPI_CCR_ADMODE_SHIFT);
284 }
285
286 if (op->dummy.buswidth && op->dummy.nbytes)
287 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
288 << STM32_QSPI_CCR_DCYC_SHIFT);
289
290 if (op->data.nbytes)
291 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
292 << STM32_QSPI_CCR_DMODE_SHIFT);
293
294 writel(ccr, &priv->regs->ccr);
295
296 if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
297 writel(op->addr.val, &priv->regs->ar);
298
299 ret = _stm32_qspi_tx(priv, op, mode);
300 /*
301 * Abort in:
302 * -error case
303 * -read memory map: prefetching must be stopped if we read the last
304 * byte of device (device size - fifo size). like device size is not
305 * knows, the prefetching is always stop.
306 */
307 if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
308 goto abort;
309
310 /* Wait end of tx in indirect mode */
311 ret = _stm32_qspi_wait_cmd(priv, op);
312 if (ret)
313 goto abort;
314
315 return 0;
316
317 abort:
318 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
319
320 /* Wait clear of abort bit by hw */
321 timeout = readl_poll_timeout(&priv->regs->cr, cr,
322 !(cr & STM32_QSPI_CR_ABORT),
323 STM32_ABT_TIMEOUT_US);
324
325 writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
326
327 if (ret || timeout)
328 dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
329
330 return ret;
331 }
332
stm32_qspi_probe(struct udevice * bus)333 static int stm32_qspi_probe(struct udevice *bus)
334 {
335 struct stm32_qspi_priv *priv = dev_get_priv(bus);
336 struct resource res;
337 struct clk clk;
338 struct reset_ctl reset_ctl;
339 int ret;
340
341 ret = dev_read_resource_byname(bus, "qspi", &res);
342 if (ret) {
343 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
344 return ret;
345 }
346
347 priv->regs = (struct stm32_qspi_regs *)res.start;
348
349 ret = dev_read_resource_byname(bus, "qspi_mm", &res);
350 if (ret) {
351 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
352 return ret;
353 }
354
355 priv->mm_base = (void __iomem *)res.start;
356
357 priv->mm_size = resource_size(&res);
358 if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
359 return -EINVAL;
360
361 dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
362 priv->regs, priv->mm_base, priv->mm_size);
363
364 ret = clk_get_by_index(bus, 0, &clk);
365 if (ret < 0)
366 return ret;
367
368 ret = clk_enable(&clk);
369 if (ret) {
370 dev_err(bus, "failed to enable clock\n");
371 return ret;
372 }
373
374 priv->clock_rate = clk_get_rate(&clk);
375 if (!priv->clock_rate) {
376 clk_disable(&clk);
377 return -EINVAL;
378 }
379
380 ret = reset_get_by_index(bus, 0, &reset_ctl);
381 if (ret) {
382 if (ret != -ENOENT) {
383 dev_err(bus, "failed to get reset\n");
384 clk_disable(&clk);
385 return ret;
386 }
387 } else {
388 /* Reset QSPI controller */
389 reset_assert(&reset_ctl);
390 udelay(2);
391 reset_deassert(&reset_ctl);
392 }
393
394 priv->cs_used = -1;
395
396 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
397
398 /* Set dcr fsize to max address */
399 setbits_le32(&priv->regs->dcr,
400 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
401
402 return 0;
403 }
404
stm32_qspi_claim_bus(struct udevice * dev)405 static int stm32_qspi_claim_bus(struct udevice *dev)
406 {
407 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
408 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
409 int slave_cs = slave_plat->cs;
410
411 if (slave_cs >= STM32_QSPI_MAX_CHIP)
412 return -ENODEV;
413
414 if (priv->cs_used != slave_cs) {
415 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
416
417 priv->cs_used = slave_cs;
418
419 if (flash->initialized) {
420 /* Set the configuration: speed + cs */
421 writel(flash->cr, &priv->regs->cr);
422 writel(flash->dcr, &priv->regs->dcr);
423 } else {
424 /* Set chip select */
425 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
426 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
427
428 /* Save the configuration: speed + cs */
429 flash->cr = readl(&priv->regs->cr);
430 flash->dcr = readl(&priv->regs->dcr);
431
432 flash->initialized = true;
433 }
434 }
435
436 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
437
438 return 0;
439 }
440
stm32_qspi_release_bus(struct udevice * dev)441 static int stm32_qspi_release_bus(struct udevice *dev)
442 {
443 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
444
445 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
446
447 return 0;
448 }
449
stm32_qspi_set_speed(struct udevice * bus,uint speed)450 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
451 {
452 struct stm32_qspi_priv *priv = dev_get_priv(bus);
453 u32 qspi_clk = priv->clock_rate;
454 u32 prescaler = 255;
455 u32 csht;
456 int ret;
457
458 if (speed > 0) {
459 prescaler = 0;
460 if (qspi_clk) {
461 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
462 if (prescaler > 255)
463 prescaler = 255;
464 }
465 }
466
467 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
468 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
469
470 ret = _stm32_qspi_wait_for_not_busy(priv);
471 if (ret)
472 return ret;
473
474 clrsetbits_le32(&priv->regs->cr,
475 STM32_QSPI_CR_PRESCALER_MASK <<
476 STM32_QSPI_CR_PRESCALER_SHIFT,
477 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
478
479 clrsetbits_le32(&priv->regs->dcr,
480 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
481 csht << STM32_QSPI_DCR_CSHT_SHIFT);
482
483 dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
484 (qspi_clk / (prescaler + 1)));
485
486 return 0;
487 }
488
stm32_qspi_set_mode(struct udevice * bus,uint mode)489 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
490 {
491 struct stm32_qspi_priv *priv = dev_get_priv(bus);
492 int ret;
493 const char *str_rx, *str_tx;
494
495 ret = _stm32_qspi_wait_for_not_busy(priv);
496 if (ret)
497 return ret;
498
499 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
500 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
501 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
502 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
503 else
504 return -ENODEV;
505
506 if (mode & SPI_CS_HIGH)
507 return -ENODEV;
508
509 if (mode & SPI_RX_QUAD)
510 str_rx = "quad";
511 else if (mode & SPI_RX_DUAL)
512 str_rx = "dual";
513 else
514 str_rx = "single";
515
516 if (mode & SPI_TX_QUAD)
517 str_tx = "quad";
518 else if (mode & SPI_TX_DUAL)
519 str_tx = "dual";
520 else
521 str_tx = "single";
522
523 dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
524 priv->regs, mode, str_rx, str_tx);
525
526 return 0;
527 }
528
529 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
530 .exec_op = stm32_qspi_exec_op,
531 };
532
533 static const struct dm_spi_ops stm32_qspi_ops = {
534 .claim_bus = stm32_qspi_claim_bus,
535 .release_bus = stm32_qspi_release_bus,
536 .set_speed = stm32_qspi_set_speed,
537 .set_mode = stm32_qspi_set_mode,
538 .mem_ops = &stm32_qspi_mem_ops,
539 };
540
541 static const struct udevice_id stm32_qspi_ids[] = {
542 { .compatible = "st,stm32f469-qspi" },
543 { }
544 };
545
546 U_BOOT_DRIVER(stm32_qspi) = {
547 .name = "stm32_qspi",
548 .id = UCLASS_SPI,
549 .of_match = stm32_qspi_ids,
550 .ops = &stm32_qspi_ops,
551 .priv_auto = sizeof(struct stm32_qspi_priv),
552 .probe = stm32_qspi_probe,
553 };
554