1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <log.h>
10 #include <usb.h>
11 #include <errno.h>
12 #include <wait_bit.h>
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <linux/delay.h>
16 #include <usb/ehci-ci.h>
17 #include <asm/io.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sys_proto.h>
22 #include <dm.h>
23 #include <asm/mach-types.h>
24 #include <power/regulator.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/phy.h>
27
28 #include "ehci.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #define USB_OTGREGS_OFFSET 0x000
33 #define USB_H1REGS_OFFSET 0x200
34 #define USB_H2REGS_OFFSET 0x400
35 #define USB_H3REGS_OFFSET 0x600
36 #define USB_OTHERREGS_OFFSET 0x800
37
38 #define USB_H1_CTRL_OFFSET 0x04
39
40 #define USBPHY_CTRL 0x00000030
41 #define USBPHY_CTRL_SET 0x00000034
42 #define USBPHY_CTRL_CLR 0x00000038
43 #define USBPHY_CTRL_TOG 0x0000003c
44
45 #define USBPHY_PWD 0x00000000
46 #define USBPHY_CTRL_SFTRST 0x80000000
47 #define USBPHY_CTRL_CLKGATE 0x40000000
48 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
49 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
50 #define USBPHY_CTRL_OTG_ID 0x08000000
51
52 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
53 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
54
55 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
56 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
57 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
58 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
59
60 #define USBNC_OFFSET 0x200
61 #define USBNC_PHY_STATUS_OFFSET 0x23C
62 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
63 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
64 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
65 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
66 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
67
68 /* USBCMD */
69 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
70 #define UCMD_RESET (1 << 1) /* controller reset */
71
72 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
73 #ifndef CONFIG_MXC_USB_PORTSC
74 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
75 #endif
76
77 /* Base address for this IP block is 0x02184800 */
78 struct usbnc_regs {
79 u32 ctrl[4]; /* otg/host1-3 */
80 u32 uh2_hsic_ctrl;
81 u32 uh3_hsic_ctrl;
82 u32 otg_phy_ctrl_0;
83 u32 uh1_phy_ctrl_0;
84 u32 reserve1[4];
85 u32 phy_cfg1;
86 u32 phy_cfg2;
87 u32 reserve2;
88 u32 phy_status;
89 u32 reserve3[4];
90 u32 adp_cfg1;
91 u32 adp_cfg2;
92 u32 adp_status;
93 };
94
95 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
usb_power_config_mx6(struct anatop_regs __iomem * anatop,int anatop_bits_index)96 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
97 int anatop_bits_index)
98 {
99 void __iomem *chrg_detect;
100 void __iomem *pll_480_ctrl_clr;
101 void __iomem *pll_480_ctrl_set;
102
103 if (!is_mx6())
104 return;
105
106 switch (anatop_bits_index) {
107 case 0:
108 chrg_detect = &anatop->usb1_chrg_detect;
109 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
110 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
111 break;
112 case 1:
113 chrg_detect = &anatop->usb2_chrg_detect;
114 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
115 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
116 break;
117 default:
118 return;
119 }
120 /*
121 * Some phy and power's special controls
122 * 1. The external charger detector needs to be disabled
123 * or the signal at DP will be poor
124 * 2. The PLL's power and output to usb
125 * is totally controlled by IC, so the Software only needs
126 * to enable them at initializtion.
127 */
128 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
129 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
130 chrg_detect);
131
132 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
133 pll_480_ctrl_clr);
134
135 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
136 ANADIG_USB2_PLL_480_CTRL_POWER |
137 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
138 pll_480_ctrl_set);
139 }
140 #else
141 static void __maybe_unused
usb_power_config_mx6(void * anatop,int anatop_bits_index)142 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
143 #endif
144
145 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
usb_power_config_mx7(struct usbnc_regs * usbnc)146 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
147 {
148 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
149
150 if (!is_mx7())
151 return;
152
153 /*
154 * Clear the ACAENB to enable usb_otg_id detection,
155 * otherwise it is the ACA detection enabled.
156 */
157 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
158 }
159 #else
160 static void __maybe_unused
usb_power_config_mx7(void * usbnc)161 usb_power_config_mx7(void *usbnc) { }
162 #endif
163
164 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
usb_power_config_mx7ulp(struct usbphy_regs __iomem * usbphy)165 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
166 {
167 if (!is_mx7ulp())
168 return;
169
170 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
171 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
172 &usbphy->usb1_chrg_detect);
173
174 scg_enable_usb_pll(true);
175 }
176 #else
177 static void __maybe_unused
usb_power_config_mx7ulp(void * usbphy)178 usb_power_config_mx7ulp(void *usbphy) { }
179 #endif
180
181 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
182 static const unsigned phy_bases[] = {
183 USB_PHY0_BASE_ADDR,
184 #if defined(USB_PHY1_BASE_ADDR)
185 USB_PHY1_BASE_ADDR,
186 #endif
187 };
188
189 #if !defined(CONFIG_PHY)
usb_internal_phy_clock_gate(void __iomem * phy_reg,int on)190 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
191 {
192 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
193 writel(USBPHY_CTRL_CLKGATE, phy_reg);
194 }
195
196 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(struct usb_ehci * ehci,void __iomem * phy_reg)197 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
198 {
199 void __iomem *phy_ctrl;
200 void __iomem *usb_cmd;
201 int ret;
202
203 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
204 usb_cmd = (void __iomem *)&ehci->usbcmd;
205
206 /* Stop then Reset */
207 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
208 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
209 if (ret)
210 return ret;
211
212 setbits_le32(usb_cmd, UCMD_RESET);
213 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
214 if (ret)
215 return ret;
216
217 /* Reset USBPHY module */
218 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
219 udelay(10);
220
221 /* Remove CLKGATE and SFTRST */
222 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
223 udelay(10);
224
225 /* Power up the PHY */
226 writel(0, phy_reg + USBPHY_PWD);
227 /* enable FS/LS device */
228 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
229 USBPHY_CTRL_ENUTMILEVEL3);
230
231 return 0;
232 }
233 #endif
234
usb_phy_mode(int port)235 int usb_phy_mode(int port)
236 {
237 void __iomem *phy_reg;
238 void __iomem *phy_ctrl;
239 u32 val;
240
241 phy_reg = (void __iomem *)phy_bases[port];
242 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
243
244 val = readl(phy_ctrl);
245
246 if (val & USBPHY_CTRL_OTG_ID)
247 return USB_INIT_DEVICE;
248 else
249 return USB_INIT_HOST;
250 }
251
252 #elif defined(CONFIG_MX7)
usb_phy_mode(int port)253 int usb_phy_mode(int port)
254 {
255 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
256 (0x10000 * port) + USBNC_OFFSET);
257 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
258 u32 val;
259
260 val = readl(status);
261
262 if (val & USBNC_PHYSTATUS_ID_DIG)
263 return USB_INIT_DEVICE;
264 else
265 return USB_INIT_HOST;
266 }
267 #endif
268
269 #if !defined(CONFIG_PHY)
270 /* Should be done in the MXS PHY driver */
usb_oc_config(struct usbnc_regs * usbnc,int index)271 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
272 {
273 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
274
275 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
276 /* mx6qarm2 seems to required a different setting*/
277 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
278 #else
279 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
280 #endif
281
282 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
283
284 /* Set power polarity to high active */
285 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
286 setbits_le32(ctrl, UCTRL_PWR_POL);
287 #else
288 clrbits_le32(ctrl, UCTRL_PWR_POL);
289 #endif
290 }
291 #endif
292
293 #if !CONFIG_IS_ENABLED(DM_USB)
294 /**
295 * board_usb_phy_mode - override usb phy mode
296 * @port: usb host/otg port
297 *
298 * Target board specific, override usb_phy_mode.
299 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
300 * left disconnected in this case usb_phy_mode will not be able to identify
301 * the phy mode that usb port is used.
302 * Machine file overrides board_usb_phy_mode.
303 *
304 * Return: USB_INIT_DEVICE or USB_INIT_HOST
305 */
board_usb_phy_mode(int port)306 int __weak board_usb_phy_mode(int port)
307 {
308 return usb_phy_mode(port);
309 }
310
311 /**
312 * board_ehci_hcd_init - set usb vbus voltage
313 * @port: usb otg port
314 *
315 * Target board specific, setup iomux pad to setup supply vbus voltage
316 * for usb otg port. Machine board file overrides board_ehci_hcd_init
317 *
318 * Return: 0 Success
319 */
board_ehci_hcd_init(int port)320 int __weak board_ehci_hcd_init(int port)
321 {
322 return 0;
323 }
324
325 /**
326 * board_ehci_power - enables/disables usb vbus voltage
327 * @port: usb otg port
328 * @on: on/off vbus voltage
329 *
330 * Enables/disables supply vbus voltage for usb otg port.
331 * Machine board file overrides board_ehci_power
332 *
333 * Return: 0 Success
334 */
board_ehci_power(int port,int on)335 int __weak board_ehci_power(int port, int on)
336 {
337 return 0;
338 }
339
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)340 int ehci_hcd_init(int index, enum usb_init_type init,
341 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
342 {
343 enum usb_init_type type;
344 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
345 u32 controller_spacing = 0x200;
346 struct anatop_regs __iomem *anatop =
347 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
348 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
349 USB_OTHERREGS_OFFSET);
350 #elif defined(CONFIG_MX7)
351 u32 controller_spacing = 0x10000;
352 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
353 (0x10000 * index) + USBNC_OFFSET);
354 #elif defined(CONFIG_MX7ULP)
355 u32 controller_spacing = 0x10000;
356 struct usbphy_regs __iomem *usbphy =
357 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
358 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
359 (0x10000 * index) + USBNC_OFFSET);
360 #endif
361 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
362 (controller_spacing * index));
363 int ret;
364
365 if (index > 3)
366 return -EINVAL;
367
368 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
369 if (usb_fused((ulong)ehci)) {
370 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
371 (ulong)ehci);
372 return -ENODEV;
373 }
374 }
375
376 enable_usboh3_clk(1);
377 mdelay(1);
378
379 /* Do board specific initialization */
380 ret = board_ehci_hcd_init(index);
381 if (ret) {
382 enable_usboh3_clk(0);
383 return ret;
384 }
385
386 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
387 usb_power_config_mx6(anatop, index);
388 #elif defined (CONFIG_MX7)
389 usb_power_config_mx7(usbnc);
390 #elif defined (CONFIG_MX7ULP)
391 usb_power_config_mx7ulp(usbphy);
392 #endif
393
394 usb_oc_config(usbnc, index);
395
396 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
397 if (index < ARRAY_SIZE(phy_bases)) {
398 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
399 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
400 }
401 #endif
402
403 type = board_usb_phy_mode(index);
404
405 if (hccr && hcor) {
406 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
407 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
408 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
409 }
410
411 if ((type == init) || (type == USB_INIT_DEVICE))
412 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
413 if (type != init)
414 return -ENODEV;
415 if (type == USB_INIT_DEVICE)
416 return 0;
417
418 setbits_le32(&ehci->usbmode, CM_HOST);
419 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
420 setbits_le32(&ehci->portsc, USB_EN);
421
422 mdelay(10);
423
424 return 0;
425 }
426
ehci_hcd_stop(int index)427 int ehci_hcd_stop(int index)
428 {
429 return 0;
430 }
431 #else
432 struct ehci_mx6_priv_data {
433 struct ehci_ctrl ctrl;
434 struct usb_ehci *ehci;
435 struct udevice *vbus_supply;
436 struct clk clk;
437 struct phy phy;
438 enum usb_init_type init_type;
439 enum usb_phy_interface phy_type;
440 #if !defined(CONFIG_PHY)
441 int portnr;
442 void __iomem *phy_addr;
443 void __iomem *misc_addr;
444 void __iomem *anatop_addr;
445 #endif
446 };
447
mx6_portsc(enum usb_phy_interface phy_type)448 static u32 mx6_portsc(enum usb_phy_interface phy_type)
449 {
450 switch (phy_type) {
451 case USBPHY_INTERFACE_MODE_UTMI:
452 return PORT_PTS_UTMI;
453 case USBPHY_INTERFACE_MODE_UTMIW:
454 return PORT_PTS_UTMI | PORT_PTS_PTW;
455 case USBPHY_INTERFACE_MODE_ULPI:
456 return PORT_PTS_ULPI;
457 case USBPHY_INTERFACE_MODE_SERIAL:
458 return PORT_PTS_SERIAL;
459 case USBPHY_INTERFACE_MODE_HSIC:
460 return PORT_PTS_HSIC;
461 default:
462 return CONFIG_MXC_USB_PORTSC;
463 }
464 }
465
mx6_init_after_reset(struct ehci_ctrl * dev)466 static int mx6_init_after_reset(struct ehci_ctrl *dev)
467 {
468 struct ehci_mx6_priv_data *priv = dev->priv;
469 enum usb_init_type type = priv->init_type;
470 struct usb_ehci *ehci = priv->ehci;
471
472 #if !defined(CONFIG_PHY)
473 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
474 usb_power_config_mx7(priv->misc_addr);
475 usb_power_config_mx7ulp(priv->phy_addr);
476
477 usb_oc_config(priv->misc_addr, priv->portnr);
478
479 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
480 usb_internal_phy_clock_gate(priv->phy_addr, 1);
481 usb_phy_enable(ehci, priv->phy_addr);
482 #endif
483 #endif
484
485 #if CONFIG_IS_ENABLED(DM_REGULATOR)
486 if (priv->vbus_supply) {
487 int ret;
488 ret = regulator_set_enable(priv->vbus_supply,
489 (type == USB_INIT_DEVICE) ?
490 false : true);
491 if (ret && ret != -ENOSYS) {
492 printf("Error enabling VBUS supply (ret=%i)\n", ret);
493 return ret;
494 }
495 }
496 #endif
497
498 if (type == USB_INIT_DEVICE)
499 return 0;
500
501 setbits_le32(&ehci->usbmode, CM_HOST);
502 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
503 setbits_le32(&ehci->portsc, USB_EN);
504
505 mdelay(10);
506
507 return 0;
508 }
509
510 static const struct ehci_ops mx6_ehci_ops = {
511 .init_after_reset = mx6_init_after_reset
512 };
513
ehci_usb_phy_mode(struct udevice * dev)514 static int ehci_usb_phy_mode(struct udevice *dev)
515 {
516 struct usb_plat *plat = dev_get_plat(dev);
517 void *__iomem addr = dev_read_addr_ptr(dev);
518 void *__iomem phy_ctrl, *__iomem phy_status;
519 const void *blob = gd->fdt_blob;
520 int offset = dev_of_offset(dev), phy_off;
521 u32 val;
522
523 /*
524 * About fsl,usbphy, Refer to
525 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
526 */
527 if (is_mx6() || is_mx7ulp() || is_imxrt()) {
528 phy_off = fdtdec_lookup_phandle(blob,
529 offset,
530 "fsl,usbphy");
531 if (phy_off < 0)
532 return -EINVAL;
533
534 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
535 "reg");
536 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
537 return -EINVAL;
538
539 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
540 val = readl(phy_ctrl);
541
542 if (val & USBPHY_CTRL_OTG_ID)
543 plat->init_type = USB_INIT_DEVICE;
544 else
545 plat->init_type = USB_INIT_HOST;
546 } else if (is_mx7()) {
547 phy_status = (void __iomem *)(addr +
548 USBNC_PHY_STATUS_OFFSET);
549 val = readl(phy_status);
550
551 if (val & USBNC_PHYSTATUS_ID_DIG)
552 plat->init_type = USB_INIT_DEVICE;
553 else
554 plat->init_type = USB_INIT_HOST;
555 } else {
556 return -EINVAL;
557 }
558
559 return 0;
560 }
561
ehci_usb_of_to_plat(struct udevice * dev)562 static int ehci_usb_of_to_plat(struct udevice *dev)
563 {
564 struct usb_plat *plat = dev_get_plat(dev);
565 enum usb_dr_mode dr_mode;
566
567 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
568
569 switch (dr_mode) {
570 case USB_DR_MODE_HOST:
571 plat->init_type = USB_INIT_HOST;
572 break;
573 case USB_DR_MODE_PERIPHERAL:
574 plat->init_type = USB_INIT_DEVICE;
575 break;
576 case USB_DR_MODE_OTG:
577 case USB_DR_MODE_UNKNOWN:
578 return ehci_usb_phy_mode(dev);
579 };
580
581 return 0;
582 }
583
mx6_parse_dt_addrs(struct udevice * dev)584 static int mx6_parse_dt_addrs(struct udevice *dev)
585 {
586 #if !defined(CONFIG_PHY)
587 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
588 int phy_off, misc_off;
589 const void *blob = gd->fdt_blob;
590 int offset = dev_of_offset(dev);
591 void *__iomem addr;
592
593 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
594 if (phy_off < 0) {
595 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
596 if (phy_off < 0)
597 return -EINVAL;
598 }
599
600 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
601 if (misc_off < 0)
602 return -EINVAL;
603
604 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
605 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
606 addr = NULL;
607
608 priv->phy_addr = addr;
609
610 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
611 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
612 return -EINVAL;
613
614 priv->misc_addr = addr;
615
616 #if defined(CONFIG_MX6)
617 int anatop_off, ret, devnump;
618
619 ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
620 phy_off, &devnump);
621 if (ret < 0)
622 return ret;
623 priv->portnr = devnump;
624
625 /* Resolve ANATOP offset through USB PHY node */
626 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
627 if (anatop_off < 0)
628 return -EINVAL;
629
630 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
631 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
632 return -EINVAL;
633
634 priv->anatop_addr = addr;
635 #endif
636 #endif
637 return 0;
638 }
639
ehci_usb_probe(struct udevice * dev)640 static int ehci_usb_probe(struct udevice *dev)
641 {
642 struct usb_plat *plat = dev_get_plat(dev);
643 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
644 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
645 enum usb_init_type type = plat->init_type;
646 struct ehci_hccr *hccr;
647 struct ehci_hcor *hcor;
648 int ret;
649
650 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
651 if (usb_fused((ulong)ehci)) {
652 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
653 (ulong)ehci);
654 return -ENODEV;
655 }
656 }
657
658 ret = mx6_parse_dt_addrs(dev);
659 if (ret)
660 return ret;
661
662 priv->ehci = ehci;
663 priv->init_type = type;
664 priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
665
666 #if CONFIG_IS_ENABLED(CLK)
667 ret = clk_get_by_index(dev, 0, &priv->clk);
668 if (ret < 0)
669 return ret;
670
671 ret = clk_enable(&priv->clk);
672 if (ret)
673 return ret;
674 #else
675 /* Compatibility with DM_USB and !CLK */
676 enable_usboh3_clk(1);
677 mdelay(1);
678 #endif
679
680 #if CONFIG_IS_ENABLED(DM_REGULATOR)
681 ret = device_get_supply_regulator(dev, "vbus-supply",
682 &priv->vbus_supply);
683 if (ret)
684 debug("%s: No vbus supply\n", dev->name);
685 #endif
686
687 #if !defined(CONFIG_PHY)
688 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
689 usb_power_config_mx7(priv->misc_addr);
690 usb_power_config_mx7ulp(priv->phy_addr);
691
692 usb_oc_config(priv->misc_addr, priv->portnr);
693
694 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
695 usb_internal_phy_clock_gate(priv->phy_addr, 1);
696 usb_phy_enable(ehci, priv->phy_addr);
697 #endif
698 #endif
699
700 #if CONFIG_IS_ENABLED(DM_REGULATOR)
701 if (priv->vbus_supply) {
702 ret = regulator_set_enable(priv->vbus_supply,
703 (type == USB_INIT_DEVICE) ?
704 false : true);
705 if (ret && ret != -ENOSYS) {
706 printf("Error enabling VBUS supply (ret=%i)\n", ret);
707 goto err_clk;
708 }
709 }
710 #endif
711
712 if (priv->init_type == USB_INIT_HOST) {
713 setbits_le32(&ehci->usbmode, CM_HOST);
714 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
715 setbits_le32(&ehci->portsc, USB_EN);
716 }
717
718 mdelay(10);
719
720 #if defined(CONFIG_PHY)
721 ret = ehci_setup_phy(dev, &priv->phy, 0);
722 if (ret)
723 goto err_regulator;
724 #endif
725
726 hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
727 hcor = (struct ehci_hcor *)((uintptr_t)hccr +
728 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
729
730 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
731 if (ret)
732 goto err_phy;
733
734 return ret;
735
736 err_phy:
737 #if defined(CONFIG_PHY)
738 ehci_shutdown_phy(dev, &priv->phy);
739 err_regulator:
740 #endif
741 #if CONFIG_IS_ENABLED(DM_REGULATOR)
742 if (priv->vbus_supply)
743 regulator_set_enable(priv->vbus_supply, false);
744 err_clk:
745 #endif
746 #if CONFIG_IS_ENABLED(CLK)
747 clk_disable(&priv->clk);
748 #else
749 /* Compatibility with DM_USB and !CLK */
750 enable_usboh3_clk(0);
751 #endif
752 return ret;
753 }
754
ehci_usb_remove(struct udevice * dev)755 int ehci_usb_remove(struct udevice *dev)
756 {
757 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
758
759 ehci_deregister(dev);
760
761 #if defined(CONFIG_PHY)
762 ehci_shutdown_phy(dev, &priv->phy);
763 #endif
764
765 #if CONFIG_IS_ENABLED(DM_REGULATOR)
766 if (priv->vbus_supply)
767 regulator_set_enable(priv->vbus_supply, false);
768 #endif
769
770 #if CONFIG_IS_ENABLED(CLK)
771 clk_disable(&priv->clk);
772 #endif
773
774 return 0;
775 }
776
777 static const struct udevice_id mx6_usb_ids[] = {
778 { .compatible = "fsl,imx27-usb" },
779 { .compatible = "fsl,imx7d-usb" },
780 { .compatible = "fsl,imxrt-usb" },
781 { }
782 };
783
784 U_BOOT_DRIVER(usb_mx6) = {
785 .name = "ehci_mx6",
786 .id = UCLASS_USB,
787 .of_match = mx6_usb_ids,
788 .of_to_plat = ehci_usb_of_to_plat,
789 .probe = ehci_usb_probe,
790 .remove = ehci_usb_remove,
791 .ops = &ehci_usb_ops,
792 .plat_auto = sizeof(struct usb_plat),
793 .priv_auto = sizeof(struct ehci_mx6_priv_data),
794 .flags = DM_FLAG_ALLOC_PRIV_DMA,
795 };
796 #endif
797