1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the esd TASREG board. 4 * 5 * (C) Copyright 2004 6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5249EVB_H 14 #define _M5249EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 27 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 28 29 /* 30 * BOOTP options 31 */ 32 #undef CONFIG_BOOTP_BOOTFILESIZE 33 34 /* 35 * Clock configuration: enable only one of the following options 36 */ 37 38 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 39 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 40 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 41 42 /* 43 * Low Level Configuration Settings 44 * (address mappings, register initial values, etc.) 45 * You should know what you are doing if you make changes here. 46 */ 47 48 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 49 #define CONFIG_SYS_MBAR2 0x80000000 50 51 /*----------------------------------------------------------------------- 52 * Definitions for initial stack pointer and data area (in DPRAM) 53 */ 54 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 55 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 56 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 57 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 58 59 #define LDS_BOARD_TEXT \ 60 . = DEFINED(env_offset) ? env_offset : .; \ 61 env/embedded.o(.text); 62 63 /*----------------------------------------------------------------------- 64 * Start addresses for the final memory configuration 65 * (Set up by the startup code) 66 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 67 */ 68 #define CONFIG_SYS_SDRAM_BASE 0x00000000 69 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 70 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 71 72 #if 0 /* test-only */ 73 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 74 #endif 75 76 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 77 78 #define CONFIG_SYS_MONITOR_LEN 0x20000 79 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 80 81 /* 82 * For booting Linux, the board info and command line data 83 * have to be in the first 8 MB of memory, since this is 84 * the maximum mapped by the Linux kernel during initialization ?? 85 */ 86 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 87 88 /*----------------------------------------------------------------------- 89 * FLASH organization 90 */ 91 #ifdef CONFIG_SYS_FLASH_CFI 92 93 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 94 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 95 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 96 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 97 # define CONFIG_SYS_FLASH_CHECKSUM 98 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 99 #endif 100 101 /*----------------------------------------------------------------------- 102 * Cache Configuration 103 */ 104 105 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 106 CONFIG_SYS_INIT_RAM_SIZE - 8) 107 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 108 CONFIG_SYS_INIT_RAM_SIZE - 4) 109 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 110 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 111 CF_ADDRMASK(2) | \ 112 CF_ACR_EN | CF_ACR_SM_ALL) 113 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 114 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 115 CF_ACR_EN | CF_ACR_SM_ALL) 116 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 117 CF_CACR_DBWE) 118 119 /*----------------------------------------------------------------------- 120 * Memory bank definitions 121 */ 122 123 /* CS0 - AMD Flash, address 0xffc00000 */ 124 #define CONFIG_SYS_CS0_BASE 0xffe00000 125 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 126 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 127 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 128 129 /* CS1 - FPGA, address 0xe0000000 */ 130 #define CONFIG_SYS_CS1_BASE 0xe0000000 131 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 132 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 133 134 /*----------------------------------------------------------------------- 135 * Port configuration 136 */ 137 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 138 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 139 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 140 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 141 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 142 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 143 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 144 145 #endif /* M5249 */ 146